5 Replies Latest reply on Oct 25, 2019 6:47 PM by LePo_1062026

    Clock Distribution Error

    DaKn_263916

      I have a clock, 1 Mhz, going into count input of UDB 16 bit cntr. In its properties I have

      checked off syced to BUS_CLK.

       

      But timing analysis errors clock is unsynced -

       

       

       

       

      I would have thought the properties box on clk would have taken care of this.

       

      But when I use an external sync component on clk, syncing to BUS_CLK, error goes away ?

       

      An aside, cannot copy to clipboard in Notice window an error ?

       

       

      Regards, Dana.

        • 1. Re: Clock Distribution Error
          BoTa_264741

          Dana,

          I believe that for reasons unknown the UDB Counter requires Clock_3 ("count") and "capture" inputs be Sync'ed to the "clock" (BUS_CLK in this case). Sometimes Sync'ing only the "count" is enough. I made a custom version of the Counter v3.0 (PSoC5), which ignores this requirement, which I can post if you need such.

          /odissey1

          • 2. Re: Clock Distribution Error
            LePo_1062026

            Dana,

             

            By design, the PSoC build process tries to force input signals to UDB blocks to be synchronized to BUS_CLK because the internal latches of the UDB are sourced by the BUS_CLK.  Synchronizing inputs to BUS_CLK virtually guarantees prevention of a condition called a meta-stable logic condition on the output of the latch taking those inputs.  See Metastability (electronics) - Wikipedia

             

            "Sync with BUS_CLK" is set by default.  Deselecting the "Sync with BUS_CLK" allows for the error to not be flagged.  This means that if meta-stability occurs, you are responsible for the results and your application can tolerate it.

             

            Len

            • 3. Re: Clock Distribution Error
              BoTa_264741

              Dana,

              Attached a demo project with standard Counter and customized Counter_ex component, which does not require to sync the "count" input when connected to a clock. The Counter_ex library can be found here:

              Phase offset and Quadrature signal generator for lock-in

              /odissey1

              Counter_01.png

              • 4. Re: Clock Distribution Error
                DaKn_263916

                So that checkoff does not force router to do the synch, it just

                controls, if path not synched, the error to be reported ?

                 

                Seems odd use of a flag. Flag implies it will fix problem, HW, at least it

                does to me.

                 

                Thanks for the reply, very helpful.

                 

                 

                Regards, Dana.

                • 5. Re: Clock Distribution Error
                  LePo_1062026

                  Dana,

                   

                  This checkoff is basically a design rule check.  It is a courtesy for the user.  The default is the preferred method to sync to the BUS_CLK especially for UDBs that need it to keep from potential output glitching.  This is a lesson Cypress learned from their PSoC1 series parts where this design rule is not enforced.

                   

                  Depending on your design it might be critical for performance to disable this synchronization but the user should be aware of the caveats of using this mode.

                   

                  Len