25FL064 CS# at powerup

jest_4523646 Oct 16, 2019 8:22 AM

Hi,

we did a little (big?) mistake in the conception around the serial flash:

on the last serie of cards (hundreds) we forgot to put a pullup resistor on the CS# (ChipSelect#) signal coming from an FPGA.

The Vcc of the Flash rises about 40 ms before the CS# rises, which is contrary to what the datasheet requires (they should rise together with CLK and Data In too)

Still the cards seem to work fine, but i wonder if there is a risk of corruption or anything alike?

Thanks for your help,

best regards,

Jeremy

1. Re: 25FL064 CS# at powerup

BushraH_91 Oct 16, 2019 10:04 AM (in response to jest_4523646)

Hello Jeremy,
Thank you for contacting Cypress Community Forum.
Yes, this violates POR timing requirements and does have potential risk. The POR timing violation may cause flash not able to be initialized correctly, thus may cause unpredictable behaviors.

Have a wonderful day
Regards,
Bushra
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2. Re: 25FL064 CS# at powerup

jest_4523646 Oct 17, 2019 12:42 AM (in response to BushraH_91)

Hi Bushrah,

Thanks so much for this quick answer!

Have a good day
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