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1. Re: S27ks0641-$skew error for CSNreg
SudheeshK_26Oct 21, 2019 11:01 PM (in response to clab_4481021)
Hi,
Please find our comment about your query below.
"The tcsm (CS# Low maximum) time is checked with this. It is covered in the spec and recommended value is 4 us. In the Verilog sdf:
(SKEW (negedge CSNeg) (posedge CSNeg) (4000))
What is the timescale you have used? SDF timescale is set to 1 ns.
About tdevice time, as usual we do not recommend changing this because we haven't tested it, but in this case I guess it is ok. There is no other way of doing it.
Other option is to use VHDL model where tdevice_VCS parameter can be changed through instantiation."
Thanks and Regards,
Sudheesh
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2. Re: S27ks0641-$skew error for CSNreg
clab_4481021 Oct 25, 2019 1:53 AM (in response to SudheeshK_26)Hi Sudheesh and thank you for your reply.
regarding the tcsm:
i am using timescale of 1ps
as we might send long write/read trans the time of the assertion of CS (low) can be 3000ns end even more - so i do not undesrtand why the tcsm was set to 1ps originally (even 1 ns is too short).
as i said - i have changed it and it solved - but i want to make sure i didn't violate something and that we wont be failing when we use the real HyperRam with its defined timing.
So how a value of tcsm=1 can be enough to deliver long streams?
best wishes,
Cluny
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3. Re: S27ks0641-$skew error for CSNreg
SudheeshK_26Dec 3, 2019 2:32 AM (in response to clab_4481021)
Hi,
Could you please let me know, whether you are using the latest Verilog model for S27KS0641 available at: https://www.cypress.com/documentation/models/verilog/s27kl0641-s27ks0641-verilog ? If not, please use this model for your simulations and let us know the results.
Thanks and Regards,Sudheesh