3 Replies Latest reply on Dec 3, 2019 2:32 AM by SudheeshK_26

    S27ks0641-$skew error for CSNreg

    clab_4481021

      Hi,

      I try to integrate the verilog model for S27ks0641 with the synopsys SSI IP.

      I got the following:

      Warning!  Timing violation
                 $skew( negedge CSNeg:414195 PS, posedge CSNeg:498597 PS,  1 : 1 PS );
                  File: s27ks0641.v, line = 369
                 Scope: ssi_tbe.mem_model
                  Time: 498597 PS

       

      I modified the value in the verilog file of tskew_CSNeg_CSNeg from 1 (tCSM) to 100000 to avoid it.

      we run in 166MHz and the time between fall(CSNeg) and rise(CSNeg) can not be 1 ps

      not sure why this value was set to such a short time?

       

      the skew command requires a time interval of 1 ps max for CS to be active - that is not enough to deliver a Hyperbus frame.

      can you please clarify?

       

      Best wishes,

      Cluny

        • 1. Re: S27ks0641-$skew error for CSNreg
          SudheeshK_26

          Hi,

           

          Please find our comment about your query below.

           

          "The tcsm (CS# Low maximum) time is checked with this. It is covered in the spec and recommended value is 4 us. In the Verilog sdf:

          (SKEW (negedge CSNeg) (posedge CSNeg) (4000))

           

          What is the timescale you have used? SDF timescale is set to 1 ns.

           

          About tdevice time, as usual we do not recommend changing this because we haven't tested it, but in this case I guess it is ok. There is no other way of doing it.

           

          Other option is to use VHDL model where tdevice_VCS parameter can be changed through instantiation."

           

          Thanks and Regards,

          Sudheesh

          • 2. Re: S27ks0641-$skew error for CSNreg
            clab_4481021

            Hi Sudheesh and thank you for your reply.

            regarding the tcsm:

            i am using timescale of 1ps

            as we might send long write/read trans the time of the assertion of CS (low) can be 3000ns end even more - so i do not undesrtand why the tcsm was set to 1ps originally (even 1 ns is too short).

             

            as i said - i have changed it and it solved - but i want to make sure i didn't violate something and that we wont be failing when we use the real HyperRam with its defined timing.

             

            So how a value of tcsm=1 can be enough to deliver long streams?

             

            best wishes,

            Cluny

            • 3. Re: S27ks0641-$skew error for CSNreg
              SudheeshK_26

              Hi,

               

              Could you please let me know, whether you are using the latest Verilog model for S27KS0641 available at: https://www.cypress.com/documentation/models/verilog/s27kl0641-s27ks0641-verilog ? If not, please use this model for your simulations and let us know the results.


              Thanks and Regards,

              Sudheesh