3 Replies Latest reply on Oct 14, 2019 12:18 AM by ApurvaS_36

    The QUAD bit of Configuration Register in S25FL256S

    mash_4487886

      Using four-wire mode to configure the FPGA, what will happen if the bit is not set to 1.Thank you.

        • 1. Re: The QUAD bit of Configuration Register in S25FL256S
          ApurvaS_36

          Hi Ma Shufang,

           

          Thank you for contacting Cypress Semiconductor.

          Could you please clarify your query a little? What do you mean by "four-wire mode"? Do you mean Single SPI mode (MOSI, MISO, CLK, CS#)? If you want to use the device in Single SPI mode you do not need to make any changes to the configuration register. The device is in Single SPI mode by default. If you want to use the device in QUAD mode, then you need to set the QUAD bit in the configuration register.

           

          The QUAD bit in the configuration register determines the mode of the device. As you can see in the datasheet (https://www.cypress.com/file/448601/download) on page 51, Table 24 shows that when the QUAD bit is set the device is in QUAD mode, where as when the bit is reset the device will be in Single or Dual SPI mode. The default state of this bit is 0 (Single SPI).

           

          Please let me know if you have any more queries.

           

          Best Regards,

          Apurva

          1 of 1 people found this helpful
          • 2. Re: The QUAD bit of Configuration Register in S25FL256S
            mash_4487886

            Hi,thanks for your reply.As you said, I need to set the QUAD bit in the Configuration Register.And I have another query now.

             

            I use the spi_ioc_transfer structure to write data from CPU to S25FL256S and write 256 Bytes each time from 0 address.The CLK is 10MHz. Since it is necessary to determine whether the register is in a busy state, I determine the state of the register before every write operation. If it's in a busy state, then wait 20 ms.But when my program runs, the register is often detected in the busy state.

            So it causes the problem of writing flash very slowly and it costs about 1 minute to write 1MBytes data.If I reduce the waiting time from 20 ms to 10 ms, then the register is busy all time in the while loop which waits 10 times.I see in the datasheet on page 5, table 1 shows that Page Programming Time is only 250us. So, what should I do and I really appreciate your help.

            • 3. Re: The QUAD bit of Configuration Register in S25FL256S
              ApurvaS_36

              Hi Ma Shufang,

               

              Thank you for your reply.

              From your reply, I can understand that you are reading the status register before every write operation. If the WIP bit of the status register is found to be set a delay of 20ms is introduced. After the write operation is performed, the status register is being read again and found to be busy after which again a delay is introduced in the code. Please correct me if I'm wrong.

               

              The recommended way to check the status of the device is to poll the WIP bit of the status register. Instead of putting a delay in the code, you should continuously read the status register value inside a while loop and the control should come out of the while loop only when the WIP bit becomes low. Introducing delay in the code will add unnecessary waiting time. Also, I would like to inform you that 250us is the typical time to write 256 bytes of data. If you are trying to write 1MBytes of data you will have to divide the data bytes in groups of 256 bytes and perform several page program operations where the (typical) time taken for each page program operation will be 250us.

               

              Please let me know if you have any further queries.

               

              Best Regards,

              Apurva