PSoC5LP : VGPIO specification

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MiNe_85951
Level 7
Level 7
Distributor - TED (Japan)
50 likes received 500 replies posted 50 solutions authored

Hi,

In the board with the customer's PSoC5LP,
Undershoot was confirmed on the input pin.

PSoC52xx Family Datasheet URL
https://www.cypress.com/file/45916/download

VGPIO is specified in "11. Electrical Specifications" on page 60 of the above data sheet.

DC input voltage on GPIO
Min : VSSD – 0.5 V
Max :VDDIO + 0.5 V

Attach customer waveform.

Vertical axis is 1V / div. Horizontal axis is 100ns / div.

Using an active probe, 0.64V is observed in less than 100ns.

I think that the specifications of the protection diode only describe DC characteristics.
Can it be judged that there is no problem in use if the spike voltage is 0.64V in 100ns or less?
This does not mean product warranty.

Or can you tell me the AC characteristics of the protective diode?

Do you have a solution if this undershoot is a problem?

Regards,

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1 Solution
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

MaMi,

I agree with Bob and TakashiM, it is best to avoid inputs over-specification.  in your case, a Schottky diode should work.

However, you might also look at place a series resistor between the input circuit and the input of the PSoC.  The most likely problem that occurs when the input voltage goes below GND (as in your case) or above VDD is something called input latch-up current.  It has to do with the FET on outputs and ESD protection diodes on inputs can be destroyed if the forward current exceeds the latch-up current.  If this happens,  it's common for it to appear as permanent a short-circuit to VSS or VDD.

For most 5V input circuits, the latch-up current is anywhere from +/-10mA to +/-200mA.  By placing a schottky diode at the pin for inputs, you should be able to 'stub' most excessive voltages.  Placing a series resistor will also limit the latch-up current.  The value of the resistor should be as high as your design can tolerate without effecting the application intent.  For both digital and analog input circuits the value depends on the frequency of changes you expect to support.  If the frequency of the input is higher, a lower value may be needed.  (eq. 1MHz => 100 ohms.)  As the input frequency lowers, you can probably tolerate a higher resistance value such as 10K.    To determine which value works best you can perform some empirical studies or you can calculate the RC equivalent value for your circuit.

The diagram below shows the ESD diode configuration in the PSoC .  It also shows the schottky diode protection for VSS and VDD along with the latch-up current limit resistor.   In your case, I recommend the resistor and the VSS protection schottky at a minimum.

pastedImage_0.png

Len

Len
"Engineering is an Art. The Art of Compromise."

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3 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Exceeding the max allowed ratings always lead to unpredictable results, so better avoid that. You may use an external schottki diode to cut the undershot.

Bob

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Hello,

As Bob mentioned, we can not say how the device behaves in case of exceeding the spec. range described in datasheet.

You must follow "DC input voltage on GPIO" described in datasheet to avoid an unforeseen issue...

And you have to care externally (from device), e.g. using schottki diode as Bob suggested.

thank you.

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Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

MaMi,

I agree with Bob and TakashiM, it is best to avoid inputs over-specification.  in your case, a Schottky diode should work.

However, you might also look at place a series resistor between the input circuit and the input of the PSoC.  The most likely problem that occurs when the input voltage goes below GND (as in your case) or above VDD is something called input latch-up current.  It has to do with the FET on outputs and ESD protection diodes on inputs can be destroyed if the forward current exceeds the latch-up current.  If this happens,  it's common for it to appear as permanent a short-circuit to VSS or VDD.

For most 5V input circuits, the latch-up current is anywhere from +/-10mA to +/-200mA.  By placing a schottky diode at the pin for inputs, you should be able to 'stub' most excessive voltages.  Placing a series resistor will also limit the latch-up current.  The value of the resistor should be as high as your design can tolerate without effecting the application intent.  For both digital and analog input circuits the value depends on the frequency of changes you expect to support.  If the frequency of the input is higher, a lower value may be needed.  (eq. 1MHz => 100 ohms.)  As the input frequency lowers, you can probably tolerate a higher resistance value such as 10K.    To determine which value works best you can perform some empirical studies or you can calculate the RC equivalent value for your circuit.

The diagram below shows the ESD diode configuration in the PSoC .  It also shows the schottky diode protection for VSS and VDD along with the latch-up current limit resistor.   In your case, I recommend the resistor and the VSS protection schottky at a minimum.

pastedImage_0.png

Len

Len
"Engineering is an Art. The Art of Compromise."
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