2 Replies Latest reply on Oct 9, 2019 1:55 AM by JaLe_2074191

    How to enable nested interrupts

    JaLe_2074191

      I have two interrups connected to the output of two SAR Sequencers (EOC). one runs fast and one slow. I want to process the data from the fast one at a higher priority. According the the ARM TRM and the Cypress PSOC5 TRM, it should be possible. However, the isr with the higher priority never runs from the isr of the lower priority. Is there something I need to do to enable "interrupt from interrupt"?

       

      My settings:

      isr_2  interrupt number 7 priority 0

      isr_3 interrupt number 8 priority 6

       

       

      How do I know it does not run while I'm in isr_3?

      I check if(*isr_2_INTC_SET_PD & (uint32)isr_2__INTC_MASK) from isr_3 and it returns true now and then.

      I have also tried setting a flag in isr_2, clearing this in the beginning of isr_3 and checking it in the end of isr_3, it is never set.

      I know both isr_2 and isr_3 are running

       

      From the TRM:

      The interrupt controller provides a priority handling feature to help a user assign priority for each interrupt. Characteristics of this feature are as follows:

      ■ Eight levels of interrupt priorities from 0 to 7.

      ■ Priority level 0 is highest and level 7 is lowest.

      ■ Priority levels set using the Interrupt Priority Registers PRI_[x].

      ■ Support of dynamic configuration of priority levels – A change of priority level of an interrupt on the fly does not affect the current execution of the same interrupt; it takes effect for the next assertion.

       

      Priority handling is very important in the following cases:

      ■ Case 1 – If an interrupt (INT B) is asserted when another interrupt (INT A) is being executed, there are three possibilities with unique handling sequences: ❐ If INT A has lower priority than INT B: 1.INT A is stopped at the point of execution. 2.The details of INT A are pushed to the stack, and INT B begins to execute. 3.After the execution of INT B, INT A execution is resumed from the point of its interruption. ❐ If INT A has higher priority than INT B: 1.INT B has to wait until INT A is executed. 2.After the execution of INT A, INT B can start execution. ❐ If INT A and INT B have equal priority: 1.If INT A is being executed; INT B has to wait until INT A is executed. After the execution of INT A, INT B can start execution. 2.If INT B is being executed; INT A has to wait until INT B is executed. After the execution of INT B, INT A can start execution

        • 1. Re: How to enable nested interrupts
          JoMe_264151

          I would suggest you to put a CyDelay() API into interrupt handler for isr_2. Because SAR is comparably slow it can be very unlikely that within the short time of handling the interrupt the second one fires. A few ms delay will be enough. This setup is only for the proof of concept.

           

          Bob

          • 2. Re: How to enable nested interrupts
            JaLe_2074191

            Thanks for answering Bob. I added a delay in isr_3 (I assume this is waht you ment, adding ms to isr_2 makes it take up 100% of cpu time) I can see interrupts from isr_3 now but also detecting pending interrupts while in isr_3. If I understand the documentation correctly, I should never be able to see the pending bit of isr_2 from isr_3 as it has lower priority number and would therefore interrupt immidiately during the isr_3 execution. Is this correct? There may be some delay between setting the interrupt as pending and triggering isr_2 that I see.