1 Reply Latest reply on Oct 8, 2019 3:37 PM by ErLi_4223826

    FM0+ CSIO S6E1C3


      Hi, there


      I've encountered an issue using the CSIO (SPI) PDL. In the attached figure (screenshot from Saleae capture), I fired 5 Mfs_Csio_SendData(Csio1, databuf, True/False), calls to write/read a SPI slave device (flash memory). The reading and writing shown in the figure of the SPI buses are all correct. I write the first byte, 0x9F to the device, and it returns 3 bytes, 0x62, 0x06, and 0x13 with me writing 3 followup dummy bytes (0xFF). Everything looks good.


      When I said "it returns 3 bytes", what I actually did was to use the same function call: Mfs_Csio_SendData(CsioCh1, au8CsioMasterTxBuf[4], FALSE); with the last argument being 'False', meaning "dummy write". In this way, the MOSI will show 'FF', as it should be, and things are working fine.


      The issue is, the returned values shown as 0x62, 0x06 and 0x13 are shifted to the right by 1 bit when I read them back using the function call: Mfs_Csio_ReceiveData(CsioCh1), so they become 0x31, 0x03 and 0x09. What Mfs_Csio_ReceiveData(CsioCh1) does is nothing but reading the register CsioCh1->RDR. I use the debugger to read the register CsioCh1->RDR, and indeed, they are the wrong values as pointed out.


      The followings are the contents of my callback function for CSIOTX:




      ** \brief  CSIO master transfer interrupt callback function


      static void CsioMasterTxIrqCallback(void)


              volatile    en_result_t tmp;




              if(u32SendCnt == 1)Mfs_Csio_SendData(CsioCh1, au8CsioMasterTxBuf[0], TRUE);


              if(u32SendCnt == 2)


                      Mfs_Csio_SendData(CsioCh1, au8CsioMasterTxBuf[1], FALSE);    // Dummy Write

                      tmp16[0] = Mfs_Csio_ReceiveData(CsioCh1);   



              if(u32SendCnt == 3)


                      Mfs_Csio_SendData(CsioCh1, au8CsioMasterTxBuf[2], FALSE);    // Dummy Write

                      tmp16[1] = Mfs_Csio_ReceiveData(CsioCh1);   



              if(u32SendCnt == 4)


                      Mfs_Csio_SendData(CsioCh1, au8CsioMasterTxBuf[3], FALSE);

                      tmp16[2] = Mfs_Csio_ReceiveData(CsioCh1);               



              if(u32SendCnt == 5)


                      Mfs_Csio_SendData(CsioCh1, au8CsioMasterTxBuf[4], FALSE);    // Dummy write

                      tmp16[3] = Mfs_Csio_ReceiveData(CsioCh1); // Read from here gives you 0



              if(u32SendCnt == 6)  



                      // Read it again.

                      while(TRUE != Mfs_Csio_GetStatus(CsioCh1, CsioTxEmpty));

                      Mfs_Csio_SendData(CsioCh1, au8CsioMasterTxBuf[4], FALSE);    // Dummy write


                      /* Wait for Master TX bus idle (until last data is sent) */

                      while(TRUE != Mfs_Csio_GetStatus(CsioCh1, CsioTxIdle));               

                      tmp16[4] = Mfs_Csio_ReceiveData(CsioCh1);   



              if(u32SendCnt == 7)



                      Mfs_Csio_DisableIrq(CsioCh1, CsioTxIrq);

                      Gpio1pin_Put( GPIO1PIN_P34, 1u);    // Chip Select Pin


                      tmp16[5] = Mfs_Csio_ReceiveData(CsioCh1);   







      Any comment/suggestion will be highly appreciated.


      Thank you.




        • 1. Re: FM0+ CSIO S6E1C3

          I figured it out myself. This issue was gone when I reversed the polarity of the clock when it is idle, i.e., stcCsio1Config.bInvertClk = TRUE. I am not sure if it is the SPI flash chip or the mcu that is the culprit. The datasheet of the SPI flash chip says it supports both Mode 0 and 3, and the signals shown on my Saleae are always correct. I am just glad that it is working now and I can continue on my work.