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Could you let us know as to where you found the reference in the 43455 section?
But as mentioned in the introduction section of AN214843, this application note is for CYW2046, CYW4325, and CYW4329.
->Does this requirement refer to a range of acceptable signal amplitudes? I.e. a 1800 mVp-p signal would be acceptable?
Yes, it specifies the range of acceptable signal amplitudes and 1800mVp-p should be acceptable.
As I mentioned above, the application note AN214843 does not explicitly mention the CYW43455 chipset.
However, in the technical document section on the CYW43455 production information page, the application note is linked in.
See the screenshot in my question above for the linked documents at the time of the question, or visit https://www.cypress.com/part/cyw43455xkubgt#technical-documents for the live product page.
Thank you for answering that question, I will implement a 1800 mVp-p clock in the design.