5 Replies Latest reply on Oct 13, 2019 11:32 PM by PradiptaB_11

    CY7C2663KV18 sync SRAM

    BrId_4495301

      Hi, I'm using CY7C2663KV18 sync SRAM and there are two pins (BWS0! and BWS1!) that I want connect to GND because I want use all data pins in write-operation. Can I connect those pins to GND or are there problems with the read-operation if they are always LOW ?

      thanks for the support

        • 1. Re: CY7C2663KV18 sync SRAM
          PradiptaB_11

          Hi Bryan,

           

          You can connect the BWS0! and BWS1! pins to ground. There will be no problems in the read operation.

           

          Thanks,

          Pradipta.

          • 2. Re: CY7C2663KV18 sync SRAM
            BrId_4495301

            Thank you Pradipta.

            I have an other question about this SRAM.
            Can I choose which pin of the address bus is the most significant or there is an order to follow?
            I see that is possibile to extend the width of the memory, but how can I extend depth?
            How I can use the 288M pin for this purpose? I have read that it is not connected to the die. What does it mean?

            Thank you for the support.
            Best regards
            Bryan

            • 3. Re: CY7C2663KV18 sync SRAM
              PradiptaB_11

              Hi Bryan,

               

              You can choose whatsoever order for the Address pins as you want. There is no predefined LSB or MSB pin for Address. It will depend on your connections. Since you will be able to read and write from the same location if that address is generated on the pins. Internally which address is accessed will not matter.

              For depth expansion you can use the port select pins. Only when the port select pins are asserted the device will perform a read or write operation depending on which port is selected. If the port select pin is not asserted then the address and data pin are ignored and no read or write will take place.

              288M pin is NC. Since it is not connected to the die it will have no impact whatsoever on the device operations.No use for this pin.

               

              Thanks and regards,

              Pradipta.

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              • 4. Re: CY7C2663KV18 sync SRAM
                BrId_4495301

                Hi Pradipta,

                thank you!

                I understood, but which pins do you mean as port select pins?

                Are you referring to BWS0! and BWS1! Pins?

                 

                Thanks,

                Bryan

                • 5. Re: CY7C2663KV18 sync SRAM
                  PradiptaB_11

                  Hi Bryan,

                   

                  The WPS# and RPS# are the port select pins. One is for write and the other is for read. If they are not asserted then a write or a read will never take place and the address and data lines will be ignored. So these two pins can be used for depth expansion as it works like a  chip select pin for the respective ports.

                   

                  Thanks,

                  Pradipta.

                  1 of 1 people found this helpful