1 Reply Latest reply on Sep 30, 2019 12:25 AM by HemanthR_06

    I2C clock stretching in CX3 during random read operation




      According to the TRM the CX3 seems to support I2C clock stretching in general. However, I couldn't find any more details about this topic so I have a couple of questions with respect to that:


      1. Does the CX3 support I2C clock stretching also in FS mode (400kHz)?
      2. Is clock stretching during random read operation supported, and if so, when should the clock be stretched? I.e. is the following procedure feasible:
        1. Master issues a START condition

        2. Master sends I2C slave address + one L bit (WRITE)

        3. Slave issues ACK to master if address matches

        4. Master sends address to be read from

        5. Slave issues ACK to master

        6. Master issues a repeated START condition

        7. Master sends I2C slave address + one H bit (READ)

        8. Slave sends ACK to master if address matches

        9. Slave stretches clock until it has the data ready
        10. Master receives data, and issues a ACK for each received byte

        11. Master stops the operation by issuing a NACK after the last byte, follow by a STOP condition


      Or should the clock rather be stretched at a different step? What is the maximum time the clock can be stretched before the master (CX3) issues a timeout?



        • 1. Re: I2C clock stretching in CX3 during random read operation



          It can be stretching at the instant where you have pointed.

          If you refer to $FX3_SDK_Installation_path$\EZ-USB FX3 SDK\1.3\firmware\fx3_sdk_1_3_4_src\sdk\firmware\src\lpp\cyu3i2c.c,

          you can see that in CyU3PI2cReceiveBytes() API, there is a do..while loop. In that loop, there is a while loop which retrieves the data from the FIFO. After the Step 8 in your comments is reached successfully, FX3 waits for the data from the slave. There is a timeout set for read operation as a whole. There is a counter 'glI2cReadTimeout' which is initialized to 0xFFFFF. If the CPU is running at 201.6MHz then the minimum timeout duration would be 5.2ms. So, if clock stretching is involved between steps 8 and 11, then it is good to complete the read operation within 5.2ms.