2 Replies Latest reply on Sep 23, 2019 11:09 PM by EktaN_26

    Asynch Path Warning with SRFF

    alfi_297226

      I get  an Asynch Path Warning that I don't understand and can't isolate further. It is caused by adding the standard SR Flip-flop component to a circuit in a PSoC 5LP design.

      Attached is an archive bundle of a debug workspace called "Asynch Debug" which contains two simple projects one with the SRFF component added downstream of a Counter component and one without the SRFF. The project with SRFF throws the Static Timing Warning and the one without it does not.

      Why does this happen?

       

      Thank You