First, I have realized you changed a Support Site. In the Inquiry Type I miss a possibility to choose something like a "technical support". "Datasheet" entry is not correct for this I think. But anyway, back to our issue. If I should post it somewhere else, let me know.
We are currently having problems with performing a software reset on the CYT2BB5/B7 devices, Our software runs on the M4 cores and we are using the BootCode provided by cypress on our M0 cores.
The software works fine standalone, after a power on reset the M0 runs to its BootCode and kicks the M4 core out of reset, the M4 then starts executing the user application.
In the case where we perform a software reset on the M4 core(by performing the following write “0xE000ED0C = 0x05FA0004;” as described in the ARM architecture manual) the M0+ resets as well and ends up landing somewhere in the Flash Supervisory Region (0x1700,0000) and does not bring the M4 core out of reset.
The ROM Boot flow chart as described in the Traveo II Architecture TRM seems to work for the PowerOn reset but not for the SOC reset which is somehow triggered by an M4 core software reset.
The question is how is a software reset on the M4 core supposed to be handled by the hardware? What needs has to be done to get the user application running again on the M4 core after a softreset?
With best regards,