1 Reply Latest reply on Sep 17, 2020 7:07 AM by SuAg_4382401

    Memory Protection Unit feature implementation for Traveo 2M series. (CYT2B95CAE).


      Need sample configurations for implementation of MPU and SMPU feature for CYT2B95CAE series controller.

      The application note, however mentions usage of MPU_RNR, MPU_TYPE and other such registers (As per Arm_V7 reference manual).

      But there are other registers available in the respective Registers specific manual which has no mention as per the application note example. (ADDR and ATT registers).

      Need clarification on usage of the above mentioned registers and base addresses required to configure the MPU and SMPU feature support.