10 Replies Latest reply on Oct 9, 2019 10:04 PM by YatheeshK_36

    FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills

    SiTe_3990886

      Hello everybody,

       

      I'm currently designing a board which involves USB communication from an FPGA through an FX2LP.

       

      I aim to interface my FPGA to the FX2 with the default Slave FIFO Interface.

      The application note AN61345 describes this usage of the FX2, but I have a question about the read procedure. This application note explains that:

      • When the FIFO empty flag is de-asserted (means there is data in the FIFO), the FPGA asserts SLOE and SLRD signals to read data from FIFO
      • When the FIFO empty flag is asserted again (means no data anymore in the FIFO), the FPGA stops asserting SLOE and SLRD => end of read sequence

       

      The Slave FIFO Interface can operate at a maximum of 48 MHz, with a bus data width (FD) of 16 bits. This means the FPGA can read up to 768 Mbps from the FIFO.

      If the FPGA empties the FIFO faster than the USB bus fills it (at 480 Mbps), the FIFO empty flag will be asserted before the end of the USB transfer.

       

      How can I distinguish between those two situations: ?

      • FIFO empty flag is asserted because the whole USB transfer has ended and FIFO has been emptied
      • FIFO empty flag is asserted because the FPGA emptied the FIFO faster than the USB bus fills it, but the USB transfer has not ended

       

      For write sequences, the FPGA signals end of transfers with PKTEND signal, but there is no other equivalent signal for read sequences.

       

      Thank you for your help.

        • 1. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
          YatheeshK_36

          Hello,

           

          The data transfer to FIFO happens in packet size. So, the data is not written byte by byte to the FIFO from the EP buffer. Once the buffer is full with the size of a USB packet data, the data present in the buffer is then committed to FIFO when the empty flag is de-asserted indicating that data is present in the FIFO for the master to perform a read operation.

          until the next buffer is filled (in multi-buffering) the FIFO will not have data to be read by the master.

          Please refer to section "1.18  External FIFO Interface" form the EZ-USB Technical Reference Manual.

           

          Best Regards,

          Yatheesh

          1 of 1 people found this helpful
          • 2. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
            SiTe_3990886

            Hello Yatheesh,

             

            Thank you for you quick reply. I had not noticed before that FIFO was filled by USB packets rather than byte after byte.

             

            Still, my question remains valid as I cannot figure out how I get notified of the end of a transfer.

            Let's take a simple example with a Bulk out endpoint, configured with a double buffering 512 buffer. AUTOOUT is set to 1, so, whatever the packet length, endpoint buffer is automatically committed to FIFO.

            The maximum packet size of a Bulk endpoint is 512, but a bulk transfer can be of different sizes:

            1. Bulk transfer is 500 bytes long. The payload is then 500 bytes long and transfer occurs in one frame.
            2. Bulk transfer is 512 bytes long. The 1st payload is exactly 512 bytes long, and a 2nd zero-length packet is then transmitted.
            3. Bulk transfer is 520 bytes long. The 1st payload is exactly 512 bytes long, and a 2nd 8 bytes packet is then transmitted.

             

            In case "1", my FX2 endpoint buffer is filled with 500 bytes. At the end of the transfer, data is committed to the FIFO and empty flag is cleared. Right?

            In case "2", data is committed to FIFO and empty flag is de-asserted. My FPGA can read from FIFO, but how do I know that the transfer has ended? What is the effect of the zero-length packet on the Slave FIFO interface?

            In case "3", 512 bytes of data is committed to FIFO, empty flag is de-asserted, and I presume the next 8 bytes are written to the 2nd endpoint buffer (double buffering). The FPGA can read the first 512 bytes until empty flag is asserted again. Are the last 8 bytes of data committed to the FIFO then?

             

            Thank you in advance.

            Best regards,

            Simon.

            • 3. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
              SiTe_3990886

              According to this article: FX2 Firmware Cannot Detect Zero-length Packets

              "The FX2 suppresses zero-length packet signalling in the FIFO buffer status flags...if zero-length packets need to be detected for higher level signalling, then polling on the EP2468STAT SPR register FIFO status flags will indicate packets even if zero length"

               

              If this is right, this means that there is not any way to detect the end of transfer from the Slave FIFO interface. Zero-length packet won't be signaled, and I have no clue of whether I received a 512 bytes bulk transfer, or if other data is still about to come.

               

              Could you please confirm this point?

               

              Thank you.

              • 4. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
                YatheeshK_36

                Hello,

                 

                The zero length concept comes into play during a IN transfer from the FX2LP to the host. When FX2LP IN endpoint has no data to send during an IN request and the PKTEND is activated, a zero length packet is sent to the host.

                 

                The Master should poll the status of FX2LP FIFO flags always in order to know if the data is present on the slave side, for this the master should know the number of bytes its expecting for the slave every time, as the master is initiating the transaction.

                 

                EP2468STAT register gives the status of the endpoint buffers, this can be used in manual mode when the data sent from the host needs CPU intervention (like modifying the buffer data before committing or discard the packet ).

                 

                Best Regards,

                Yatheesh 

                • 5. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
                  SiTe_3990886

                  Hello,

                   

                  • The zero length concept comes into play during a IN transfer from the FX2LP to the host. When FX2LP IN endpoint has no data to send during an IN request and the PKTEND is activated, a zero length packet is sent to the host.

                  The zero length packet is not a concept related to IN transfers of the FX2, but is part of the USB specification and used for different scenarios, including both IN and OUT transactions. The fact that FX2LP sends a ZLP (zero-length packet) to the host when it has no data to provide to an IN request is just a specific case.

                  As described in my message on 20th september, it is part of the standard to send short packet or zero-length packet from host to device to signal the end of a bulk transfer.

                   

                  • The Master should poll the status of FX2LP FIFO flags always in order to know if the data is present on the slave side, for this the master should know the number of bytes its expecting for the slave every time, as the master is initiating the transaction.

                  It is clear to me, as described in the FX2 Technical Reference Manual, that the master has to monitor the FIFO flags to know when data is available. But the master has no idea of the number of bytes that are coming. The Master does not initiate any USB transaction, but only masters FX2 FIFO interface. Both the FX2 and the FPGA represent the USB device and USB transactions are initiated by the host computer only. Knowing the number of bytes to transfer is part of the USB protocol (with the help of short and zero length packets) and the FX2 has this information. But the Master (my FPGA) does not have this information.

                  When an empty flag of the FIFO interface is asserted again, it tells me that FIFO has been emptied, but does not inform me if more data is coming for the same USB transfer.

                   

                  • EP2468STAT register gives the status of the endpoint buffers, this can be used in manual mode when the data sent from the host needs CPU intervention (like modifying the buffer data before committing or discard the packet ).

                  This is true. But when using endpoints 2,4,6,8 with FIFOs and no CPU intervention, how to be notified of the end of a USB transaction?

                   

                  Best regards,

                  Simon.

                  • 6. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
                    YatheeshK_36

                    Hello,

                     

                    The zero length packet can be detected in the USB side from the host when it is not committed to the slave FIFO side in manual mode.

                    The EP2CS bits 6:4 will have the value equal to number of packets stored in EP buffer (before committing), this will detect even the zero length packet i.e. NPAC will have a value 1 when there is only a zero length packet present in the buffer.

                     

                    EP2468STAT will indicate if the corresponding End Point is empty or full depending on the packets present in it. If a zero length packet is present the End point buffer (not yet committed) then the bit corresponding to EP2 EF is low.

                     

                    EP2BCH and EP2BCL will indicate the number of data bytes present in the data buffer(which is to be committed next).

                     

                    Consider you have sent a zero length packet from the host side. When the other the buffers in EP2 are committed to the Slave side and zero length packet is the next one, at this point of time NPAK[2:0] will have a value 1 and the BCH and BCL will display value as zero.

                    You can use a GPIO to indicate that a zero length packet is sent to the slave from the host.

                     

                    Best Regards,

                    Yatheesh

                    • 7. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
                      SiTe_3990886

                      Hello,

                       

                      Thank you for explanations about how to detect the zero-length packet in the FX2 CPU, but it is worthless using the Slave FIFO interface if I involve the CPU in the communication.

                       

                      If ONLY considering the Slave FIFO Interface with a Bulk Out endpoint and its FIFO:

                      • When the endpoint buffer is filled by the beginning of the bulk transfer, the empty flag is de-asserted.
                      • Can I consider (thanks to double buffering) that, whatever the speed I empty the FIFO from the FPGA, the "empty flag" of this FIFO will only be asserted again when the whole bulk transfer will have filled the FIFO and been emptied by FPGA? (even if the transfer consists in multiple USB packets and multiple FX2 endpoint buffer filling)

                       

                      Best regards,

                      Simon.

                      • 8. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
                        YatheeshK_36

                        Hello Simon,

                         

                        The empty flag will be asserted when there is no data in the FIFO irrespective of whether the endpoint buffer is being filled by the incoming packet or not.

                        When in a bulk transfer of larger size, if the FIFO is emptied by the FPGA before the next packet is committed to it (buffer is still being filled)

                        the FIFO empty flag will be asserted.

                         

                        Regards,

                        Yatheesh

                        • 9. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
                          SiTe_3990886

                          Thank you Yatheesh,

                           

                          From all information you gave me, it looks like I have to embed the length of my messages in them and count the bytes in the FPGA so that I know when begin and end of transfers come.

                          The flags will give me information about when to read data from out FIFO only.

                           

                          Regards,
                          Simon.

                          • 10. Re: FX2LP - How to detect "end of transfer" in FIFO read if FPGA reads faster than FIFO fills
                            YatheeshK_36

                            Hello Simon,

                             

                            Yes that is correct, the master should know the length of the data that it needs to read from the slave side and needs to poll the FIFO flags for the data availability.

                             

                            Best Regards,

                            Yatheesh