7 Replies Latest reply on Sep 18, 2019 5:52 AM by BiBi_1928986

    Random state when disabling clock output pin in PSoC 4

    OtGo_1311741

      Hi everybody,

       

      I'm using a pin to output a clock signal of 1KHz named Clock1.  I have configured the pin as Clock-Inverter in the output mode and selected External in the Out Clock option.  The clock signal output is working fine. But when I disable the signal using the function Clock1_Stop(), the pin state, instead of being 0V, sometimes becomes 5V steady.  I need the pin to be zero volts steady when I disable this clock.

       

      Anybody knows why this happens and how to fix it?  Thanks in advance.

        • 1. Re: Random state when disabling clock output pin in PSoC 4
          BiBi_1928986

          Hello.

           

          Clock1_Stop() only stops the counter from counting any further.  The counter will randomly be stopped when the output is 1 or when the output is 0.  This is just the way it works.

           

          You could try Clock1_Stop() followed by Clock1_Init().  Or, don't use Clock1_Stop() and just use Clock1_Init().  Maybe Clock1_Init() is enough.

           

          Bill

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          • 2. Re: Random state when disabling clock output pin in PSoC 4
            OtGo_1311741

            Hi,

             

            Thanks for replying.  But the clock's datasheet says when the function Clock1_Stop() is invoked, the output will be logic 0.  Also I'm using the chip CY8C4125PVI-482 so the project does not generate any Clock1_Init() function.  The problem could be related to a synchronization loss between the shutdown of the clock and the circuit that drives the pin, but I'm not sure.

            • 3. Re: Random state when disabling clock output pin in PSoC 4
              BiBi_1928986

              Hmmmmm.....

              I was thinking you were using a TCPWM component.  Now I realize you are using a Clock component.  Sorry for the confusion.

               

              I read the Clock component datasheet and saw what you saw wrt Stop().  It should go to logic 0.

               

              So, the Clock1 signal is driving the Pin output connection (I'm assuming this is the connection) and this is working.

              How do you observe this is working?

               

              What signal are you using to drive the Pin out_clk connection?

              Why not use the default HFCLK?

              Why use Clock_Inverted?

              What signal is driving Pin output connection?

               

              Sorry for all the questions.  I've made a small project and tried to emulate your design without knowing enough of the details.  I use an old version of Creator, so I can't open newer versions of Creator files.  Maybe you can attach (or insert) a screen capture of the Clock and Pin circuitry.

               

              Bill

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              • 4. Re: Random state when disabling clock output pin in PSoC 4
                OtGo_1311741

                Background:

                 

                The system has a LCD with backlight.  The backlight should be on only for few seconds or if the user presses any button of the system. To reduce the consumption, the backlight is driven by a square wave, 1 KHz 50% duty cycle.  I cannot make hardware changes to this design, only software.  Also, no free PWM or timer to perform this operation.

                 

                Screen captures:

                Pic1.jpgPic2.jpgPic3.jpgPic4.jpg

                 

                How do you observe this is working? I used an oscilloscope to verify the waveform at the output.  It is exactly the same frequency as the clock I selected for this pin.

                 

                What signal are you using to drive the Pin out_clk connection? A clock instance of 1KHz

                 

                Why not use the default HFCLK? Because the design needed a 1 KHz 50% duty cycle clock from the microcontroller. I cannot use any timer or pwm for that due to certain restrictions of these particular design.

                 

                Why use Clock_Inverted? To fix a weird thing, if I use normal clock, sometimes the pin goes to high impedance instead of 0V or 5V.  Us

                 

                What signal is driving Pin output connection? A smt MOSFET to drive a LCD backlight LED.

                 

                Here is the code to enable or disable the backlight:

                 

                if(LcdInfo.BackLightTime==0&&!Flag.MenuActive)  /* Finished backlight time or menu? */      

                {

                     if(Flag.BackLightOn)

                     {  

                          Flag.BackLightOn=0;

                          BACKLITECLOCK_Stop(); /* Disable clock*/

                      }

                }

                else

                {

                     if(!Flag.BackLightOn)   /* Backlight off ? */

                     {

                          Flag.BackLightOn=1;

                          BACKLITECLOCK_Start(); /* Enable clock */

                     }

                }

                Let me know if more info is needed.  Thanks.

                • 5. Re: Random state when disabling clock output pin in PSoC 4
                  BiBi_1928986

                  Thanks for the info.  That helped.

                  I must admit, I've never tried to clock a GPIO pin to use the clock as a data output.  I've only used it with the Sync component to synchronize GPIO's across clock domains.  BTW, on my Creator (v3.1), the GPIO (v2.10) symbol shows an input for driving the pin.  Yours does not show this input line.  Just a curious observation.

                   

                  I was able to replicate your observations.  I have exactly the same setup as the screen shots.


                  I then tried several scenario's to figure out what BACKLITECLOCK was doing.  But, I'm at a loss.  There's no good way to observe it directly since it can only be connected to the clock input of a component.

                   

                  I did however find a solution.  I hope it works for you.

                  After you Start the clock, BACKLITECLOCK_Write(1u).

                  After you Stop the clock, BACKLITECLOCK_Write(0u).

                  Because PSoC 4 excutes sooooo much faster than the 1kHz clock, the extra time it takes to execute the 'Write', should not make a difference to the output result you desire.

                   

                  I think someone from Cypress will need to respond to this Stop() dilemma not returning to logic 0.

                   

                  Bill

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                  • 6. Re: Random state when disabling clock output pin in PSoC 4
                    OtGo_1311741

                    I think I got something working.  In fact the pin has a output clock enable which lets me control the output clock.  If it is logic 1, the clock signal will be at the output of the pin.  If it is logic 0, the pin becomes zero, so I don't have to turn off the clock.

                     

                    Luckily, I could use an extra pin available as a control register to manipulate the output clock enable signal (the PSoC I'm working with does not have control registers):

                    I'll be testing but I think this may resolve the issue .

                    • 7. Re: Random state when disabling clock output pin in PSoC 4
                      BiBi_1928986

                      I like your solution.

                       

                      I found I could simplify my previous suggestion.

                      Simply BACKLITECLOCK_Start().  Then use BACKLITEPIN_Write(1) to enable the clock output.  And use, BACKLITEPIN_Write(0) to disable the clock output.  It's similar code to your solution and saves a pin.

                       

                      Note: In the INIT code, BACKLITEPIN_Write(0) then BACKLITECLOCK_Start() to avoid the clock immediately coming out of pin.

                       

                      If your application is 'power' sensitive, you would still want to stop() the clock source to save energy.

                       

                      I hope Cypress explains why Clock_Stop() does not result in logic 0 output.

                       

                      Bill

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