The number of bits sampled serially over the MIPI interface should be transmitted at the same speed or faster than that over Parallel interface of MIPI bridge.
MIPI input receives two bits per a clock. Based on active time, please calculate the number of bits it is sampled in H-Active time.
Calculate the same on MIPI configuration side. Here, the number bits transmitted to GPIF over parallel interface at Pixel clock rate (< 100 MHz).
The rate at which MIPI block transmits the parallel data should be faster (equal to) than rate at which Mipi receives over serial data.
what is mean "MIPI CS2 input timing" and "CX3 mipi interface configuration"?
H-active < H active ？
What is reasonable value about H blanking in CX3 mipi interface configuration?
Can you please provide me the entire snapshot of MIPI Receiver configuration tab. That will help me to expalin you better.
Hblanking on MIPI interface configuration depends on Parallel clock on parallel interface and width of parallel data bus.