1 Reply Latest reply on Sep 13, 2019 12:03 AM by EktaN_26

    What sort of runaway causes a reset on PSoC4000S?




      We know that there is the explanation about Watch Dog Timer in "Watchdog Timer in the PSoC® 4000 Family – KBA91373".

      Of course, in case of PSoC4000S, there is a difference in the number of WDT IRQ between PSoC4000 and PSoC4000S.

      So, we changed like below.

          /* Set the WDT interrupt vector to the WDT ISR*/

          CyIntSetVector(6, WDT_ISR);


          /* Enable WDT ISR in CPU vectors - which is caused by WDT match */



      What sort of runaway causes a reset on PSoC4000S?

      For example, In the "/* Application Code */" of KBA91373 explanation the for loop described below may also be considered as a so-called runaway

      because it is the same as the looped state after runaway.




      But, the WDT reset never happens.



      Best regards,


        • 1. Re: What sort of runaway causes a reset on PSoC4000S?

          Hello Yocchi,


          The WDT_COUNTER register provides the count value of the WDT. The WDT generates an interrupt when the count value in WDT_COUNTER equals the match value stored in the WDT_MATCH register, but it does not reset the count to '0'. Instead, the WDT keeps counting until it overflows (after 0xFFFF when the resolution is set to 16 bits) and rolls back to 0. When the count value again reaches the match value, another interrupt is generated.


          A bit named WDT_MATCH in the SRSS_INTR register is set whenever the WDT interrupt occurs. This interrupt must be cleared by writing a '1' to the WDT_MATCH bit in SRSS_INTR to reset the watchdog. If the firmware does not reset the WDT for two consecutive interrupts, the third match event will generate a hardware reset.


          For more details on this please refer to the Watchdog Timer section of the Architecture TRM for 4000S: https://www.cypress.com/file/230701/download


          Please refer to the code example: CE210292 – WDT P4S Example, for implementation of WDT for a 4000S device. I have attached the code example below.

          The code example configures the WDT to generate an interrupt every 500 ms and a reset on the third unserved interrupt (1.5 seconds).