1 Reply Latest reply on Sep 11, 2019 2:11 AM by PradiptaB_11

Hyperram diffirential CK supported IO standart

user_4064026 Sep 11, 2019 12:37 AM

Hello,

Can we feed Hyperram's CK and CK# diffirential clock buses with SSTL18I io standard? I read that Hyperram's inputs and outputs are LV-CMOS compatible on datasheet.

Do we have to use LVCMOS18 io standart for clock buses with 1.8V devices?

Best Regards,

Emre

1. Re: Hyperram diffirential CK supported IO standart

PradiptaB_11 Sep 11, 2019 2:11 AM (in response to user_4064026)

Hi,

The Hyper RAM I/Os are compatible with LV-CMOS standards. We can suggest you to use LVCMOS for best fit option.
Theoretically SSTL standard calls for an external termination. This external termination can only affect the voltage swing of the signal. The other important parameters like VIL, VIH, VOL, VOH are very similar for the two standards. If the external termination affects the voltage swing by a small fraction you can also use SSTL signalling.
I encourage you to use the IBIS model for hyper Ram and try this out.
https://community.cypress.com/external-link.jspa?url=http%3A%2F%2Fwww.cypress.com%2Fproducts%2Fhyperbus-memory

Thanks,
Pradipta.
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