The Hyper RAM I/Os are compatible with LV-CMOS standards. We can suggest you to use LVCMOS for best fit option.
Theoretically SSTL standard calls for an external termination. This external termination can only affect the voltage swing of the signal. The other important parameters like VIL, VIH, VOL, VOH are very similar for the two standards. If the external termination affects the voltage swing by a small fraction you can also use SSTL signalling.
I encourage you to use the IBIS model for hyper Ram and try this out.