4 Replies Latest reply on Sep 16, 2019 4:57 AM by DheerajK_81

    Does PSoC 6 SMIF has a unified cmd/addr/data operation?


      I'm working the SMIF interface on the PSoC 63 used in the PSoC 6 BLE Pioneer kit.


      The SMIF driver API shows separate functions to.

      • transmit a command and address (Cy_SMIF_TransmitCommand()),
      • clock possible dummy cycles(Cy_SMIF_SendDummyCycles()),
      • read or write data (Cy_SMIF_ReceiveData() or Cy_SMIF_TransmitData()).


      On some other microcontrollers we have dealt with, the command and address, dummy cycles, and data read/write are written into a data structure which is then interpreted by a subprocessor that chains the pieces of the operation together. Once set up, a single C function call to the subprocessor initiates execution.


      Does PSoC 6 SMIF have such a subprocessor or must this be done by the separate functions named above?  Of course, the PSoC 6 has both Cortex-M4 and Cortex M0+ processors.  Is this something easily coordinated through the M0+, with M4 invoking M0+ to perform the operation?


        • 1. Re: Does PSoC 6 SMIF has a unified cmd/addr/data operation?

          The SMIF driver is divided in three layers

          • cy_smif.h API
          • cy_smif_memslot.h API
          • SMIF configuration structures


          The commands you pointed out are the low level cy_smif.h API functions.




          If you use the higher level cy_smif_memslot.h API, you can use more useful functions like Cy_SMIF_Memslot_CmdRead(), Cy_SMIF_Memslot_CmdProgram()


          Please refer the PDL reference manual.  The default installation path is

          C:\Program Files (x86)\Cypress\PDL\3.0.1\doc\pdl_api_reference_manual.html

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          • 2. Re: Does PSoC 6 SMIF has a unified cmd/addr/data operation?

            It seems like we're seeing long delays between opcode/param (cmd/addr) and the data stream, on the order of an equivalent 20+ SCK (SMIF device clock) cycles between MOSI and MISO response. But really SCK is not running in that time (CS is low, as it should be).  We expect a delay corresponding to a number of dummy cycles, but this seems far beyond that.


            Note: this is with a different NOR Flash chip, not the S25FL512S chip that originally comes with the board.  Part of the reason for doing this is that there are opcodes we wish to support which  "cy_stc_smif_mem_device_cfg_t" in cy_smif_memslot.h does not support.  So we are inventing a new structure that talks to the functions in cy_smif.h . For now, we're being very conservative and running the device at 25 MHz.


            So initially, I just wanted to make sure there isn't another optimized interface that we are overlooking.


            Another way to ask this: with S25FL512S what is the expected delay between sending command and address via Cy_SMIF_TransmitCommand(), and start of receipt of data via

            Cy_SMIF_ReceiveData()? (If this is supposed to be instantaneous, then I'm doing something very wrong.)

            • 3. Re: Does PSoC 6 SMIF has a unified cmd/addr/data operation?

              If you want to reduce the software overhead, please consider to use the XIP mode.




              • 4. Re: Does PSoC 6 SMIF has a unified cmd/addr/data operation?

                Read commands may have zero to several latency cycles (dummy cycles) during which read data is read from the main flash memory array before transfer to the host. The number of latency cycles are determined by the Latency Code in the configuration register (CR[7:6]). For example, in S25FL512S memory chip, the latency table is as shown below:


                So based on your clock frequency and the command, you can configure the dummy cycles to reduce latency. This is something which is required as part of the protocol of interfacing with the memory and I think software overhead should be negligible.


                And as mentioned in the prevoius interaction, you can use XIP mode to have seamless transfer.  



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