0 Replies Latest reply on Sep 4, 2019 2:25 PM by jolo_4444126

    building a register file from sync ram

    jolo_4444126

      Working on a retro style CPU using mostly HC logic chips for fun.

       

      I wanted to try something different with the register file.

      I could build it too with 8 bit wide logic chips but thought I'd try using a small ram as the register file.

       

      The cpu in question will work as follows.

      On the low level of the clock the control lines will be setup

      - a "read" address on the register file whose value will be fed into the ALU and also

      - a "write" address on the register file where the ALU result will be written

      On the rising edge of the clock the result of the ALU is latched into the slot identified by the write address.

      The write address might be the same as the read address or a different location.

       

      So in a single cycle data is fetched from the register file and looped back into the register file.

       

      The general idea is as shown below. Though actually there are two "Read" addresses and one "write" address.

       

      The thing below is build at the moment using a bunch of +ve edge triggered latches and a demultiplexer to select the "In" and "Out" instances.

      BasicAluLoop.png

      To make the above work in a single clock cycle I need only the "In" data to be latched.

      The Write/Read Addr and the "Out" are async (combinatorial) values.

       

      I had considered putting a dual port SRAM in there instead of my edge triggered latches.

      In this setup one of the ports would be always for "write" and the other port always for "read" (just like the sides of my existing 8 bit latches).

       

      But a dual port async SRAM alone won't work as this potentially sets up a feedback loop from the "Out" back to the "In" via the ALU.

      This feedback would happen whenever the WriteAddr and ReadAddr have the same value.

      This feedback doesn't happen with my existing latches as the input to the latch only happens on the +ve edge.

      Additionally there are these SRAM caveats in the docs about problems (busy and interrupts) when the Read and Write addresses are matching.

       

      I noticed that dual port synchronous sram have this "flow through" feature and a latched input, which sounds promising.

      However, these products also seem to have a latch on the output too.

      And also latching on the addresses which will get in the way of the single cycle approach.

       

      Does anyone have advice on these devices and concerns, and in particular whether this is even possible?

       

      Thanks