Can you please refer to this document
CE213903 – PSoC 6 MCU Basic Device Firmware Update (DFU)
Please let us know if you have any queries.
You just replied giving me the same document reference (with updated title) I had the query about...
So, sorry, you have not quite answered my questions directly, which was 1. simply confirm YAY or NAY that you can add a bootloader for just one core leaving the other alone etc. (no issues over shared RAM etc.) and 2. add some specific guidance on how to do it, as I simply don't want to brick my PSoC6 module by using a trial and error approach.
Hence was looking for things spelt out for me. So, I assume then from the document that if I want to flash the M4, for example, then I simply use all instruction related to core1 (and ignore core0) in the document.
Both Cores access the same Flash memory.
If you want to only update the CM4 code, your bootloader has to be setup to only update the flash sectors assigned to the CM4 Core. So it basically is a partial update of specific flash sectors only. To see which memory is assigned to the cores please check the rom sections in the linker files for each core.
You also have to make sure that your CM0 code knows the CM4 main function address. Either by always writing to the same location or by somehow providing the address to the CM0. Otherwise your CM4 code won't start.
I am not sure if this can be easily implement with the Cypress bootloader, as I haven't worked with it yet.