PSoC 3 supports programming through the SWD interface or JTAG interface. PSoC 3 has two pins that support SWD: P1 SWDIO and P1 SWDCK, or P15 USB D+ (SWDIO) and P15 USB D– (SWDCK) pins. The internal device logic chooses between these pins automatically by detecting clock transition on SWDCK lines after the device comes out of reset. P1 can be used for XRES and USB port can be used for SWD programming as all SWD interface programmers support programming using the XRES pin provided the power is externally supplied.
Although PSoC 3 and 5 supports SWD using USBIO, it is suggested to keep a dedicated SWD 5 pin port or JTAG 10 pin port so that it is compatible with PSoC 4 or 6 (which do not support SWD using USBIO) in case of an upgrade.
For further details regarding SWD interface hardware connection please refer to '1.2.1 SWD Interface' in Page 5 of 'PSoC 3 Device Programming Specifications.'
PSoC 3 Device Programming Specifications link - https://www.cypress.com/file/44676/download
For details regarding using of USBIO as SWD pins refer the Knowledge Based Article 'Serial Wire Debug (SWD) Using USBIO Pins in PSoC® 3 and PSoC 5LP – KBA82881' - https://community.cypress.com/docs/DOC-11978
For information regarding USB bootloading refer the App Note 'PSoC® USB HID Bootloader' - https://www.cypress.com/file/45376/download
Rakshith M B