1 Reply Latest reply on Aug 27, 2019 11:25 PM by PradiptaB_11

    NVSRAM, CY14E116L-ZS25XI fail when power fluctuation occurs


      Hello CDC,


      Product: NVSRAM, CY14E116L-ZS25XI


      The NVSRAM fails when power fluctuation occurs several times and the capacitor is not able to provide more energy.


      Can you support for the following questions?


      1. Besides tHRECALL , is there another limitation to use a larger capacitor value?
      2. Per your data sheet, the STORE cycle duration (tSTORE) is 8ms, what happens if a power fluctuation occurs in the middle of a store cycle?
      3. Per your data sheet, the Power-UP RECALL duration (tHRECALL) is 30ms, what happens if a power fluctuation occurs in the middle of a power-up recall?
      4. The aging of the nvSRAM is affected by the power fluctuation?
      5. Do you consider that increasing the capacitor value is enough to avoid the failures?


      Please note that this is sensitive circuit design and is property.

      Can I have private chat?


      Thank you.

        • 1. Re: NVSRAM, CY14E116L-ZS25XI fail when power fluctuation occurs



          1) tHRECALL is the limiting factor for using a large Cap. This restriction is because the nvSRAMs are specified to be ready for access in tHRECALL time (which is 20 ms in most parts). tHRECALL is the time nvSRAM takes to complete its boot-up sequence followed by the Power Up RECALL and be ready for access. This Power Up RECALL specification guarantees that the VCAP would charge to a sufficient voltage (and charge) to ensure that the part will complete a STORE operation, should the power fail immediately after the tHRECALL time from power up. If a capacitor of value exceeding the VCAP spec is used, it is possible that the VCAP would not have charged to sufficient voltage within the tHRECALL duration. No other factor for consideration


          2) Once the store operation is initiated, internally the core is powered by the VCap pin and not the VCC pin. So even if there is power fluctuation on the line it will not affect the nvSRAM. Please note that whenever the VCC voltahe will fall below Vswitch voltage. the core will be powered by the VCAP pin instead of the VCC, store operation will be initiated (assuming one write happened after previous store) .


          3) When the VCC voltage starts to rise to its typical value if a power out happens before it crosses Vswitch there will be no effect on the device. If the power out happens after it crosses Vswitch that means during the 30 ms interval the recall operation will not be successful and the data in the SRAM is not reliable data. You will need to provide a clean power cycle to the device as shown in the datasheet for proper operation.


          4) You can perform infinite read/writes to the SRAM block of the memory. Only store cycles are limited to 1 million. there should be no issue of aging.


          5) The Cap value should be within the datasheet limits to avoid any failures. You can refer to the app note for more information on this.




          If the schematics are proprietary, you can reach me on prbd@cypress.com and we will evaluate the schematic also. You can also PM on the CDC.