2 Replies Latest reply on Aug 29, 2019 4:01 PM by EdAr_4412061

    Latency Code and Dummy Cycles for QIOR command


      I am having trouble getting the QIOR command to work.


      I am using an S25FL128L flash device for a specific design.  The maximum flash speed is 102MHz.  The S25FL256S was used in a previous design, so I'm familiar with the commands and command modes.  However, I'm baffled that I cannot get the FL-L product to go into QIOR mode.  I can run with QOR mode (1-1-4), but this mode does not have an automatic repeat capability like QIOR does.  For execute in place (XIP) the QIOR mode with automatic repeat is far more efficient than QOR.


      QIOR is formatted (1-4-4), so the opcode is serial, but the address is parallel.  In repeat mode, the opcode does not need to be sent, but the address and dummy cycles are still required (0-4-4, if you will).


      The default latency code of 0 suggests it has the same dummy cycle count as latency code 8, which suggests 8 dummy cycles (plus 2 cycles for mode byte).  Indeed, I have set CR3V[3:0] to both 0 and 8 with no difference.  Flash is accessible, but is read as repeating gibberish.


      The documentation suggests that the latency cycles of 8 plus 2 mode cycles provides a total of 10 cycles.  Since the addressing is 4-bits wide, 10 dummy cycles is the same as 5 bytes transferred, right?  Since my SPI controller uses byte count instead of cycle count, and since it includes the mode cycles in the overall dummy cycle count, 5 bytes should be the correct value, I would think.  I have tried everything from 1 byte to 8 bytes (2 mode cycles + 0 to 14 dummy cycles) with no reliable reads.  Am I misreading this somehow?


      Again, QOR works, at 102MHz, so I know I don't have a signaling problem, and yes, the device is in Quad mode (CR1V[1]).  I have tried QIOR in both non-repeating and repeating modes  with similar results.  I am using 3-byte addressing (CR2V[0]=0, with the QIOR command code EBh.  I'm must be missing something in going to QIOR mode.


      Can someone point me to what I might be missing?


      Thank you!

        • 1. Re: Latency Code and Dummy Cycles for QIOR command

          Hi Ed Arrington,


          Thank you for contacting Cypress Semiconductor.

          The explanation provided by you seems to be the correct method for QIOR command.

          1. Could you please provide us the values of the status and configuration registers after setting the correct number of latency cycles for both QOR and QIOR commands?
          2. Is it possible for you to capture the signals using a logic analyzer and send it to us? Could you please provide us the signals for the various read cycles for both QOR and QIOR commands?


          Best Regards,


          • 2. Re: Latency Code and Dummy Cycles for QIOR command



            Thank you for your help.  I apologize for the delay in responding, but we ran into several obscure hardware issues on our project that delayed working through this flash issue.


            I don't have a way to provide a logic analyzer as we kept the traces between the processor and flash as short as possible to limit the risk of cross talk, however, I do have register values.  They are:


            SR1V = 0

            CR1V = 0

            CR2V = 0x60

            CR3V = 0x78


            Those are the defaults, so I'm pleased to see that.


            All that said, we discovered a problem with the SPI interface on our board.  In some cases SPI was hampered, at other times it was fine.  Having found and fixed the SPI problem, the flash memory started working more reliably.  And in fact, we now are running QIOR with three address bytes and in high-performance mode, using the settings described above.


            The lesson here is that although the flash seemed to be broken, the interface was the real problem for us.  Live and learn.


            Thank you again for reaching out.