Hi Ed Arrington,
Thank you for contacting Cypress Semiconductor.
The explanation provided by you seems to be the correct method for QIOR command.
- Could you please provide us the values of the status and configuration registers after setting the correct number of latency cycles for both QOR and QIOR commands?
- Is it possible for you to capture the signals using a logic analyzer and send it to us? Could you please provide us the signals for the various read cycles for both QOR and QIOR commands?
Thank you for your help. I apologize for the delay in responding, but we ran into several obscure hardware issues on our project that delayed working through this flash issue.
I don't have a way to provide a logic analyzer as we kept the traces between the processor and flash as short as possible to limit the risk of cross talk, however, I do have register values. They are:
SR1V = 0
CR1V = 0
CR2V = 0x60
CR3V = 0x78
Those are the defaults, so I'm pleased to see that.
All that said, we discovered a problem with the SPI interface on our board. In some cases SPI was hampered, at other times it was fine. Having found and fixed the SPI problem, the flash memory started working more reliably. And in fact, we now are running QIOR with three address bytes and in high-performance mode, using the settings described above.
The lesson here is that although the flash seemed to be broken, the interface was the real problem for us. Live and learn.
Thank you again for reaching out.