For CCG3PA, can I have two independent sources for VDDD and VBUS_IN while having internal VBUS regulator enabled?

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JoLu_3455101
Level 4
Level 4
5 likes given 5 solutions authored 25 replies posted

Hi,

Some background first:

We have two separate power sources for VDDD (3.3V) and VBUS_IN (10-19V).  Depending on the end user, we may have both power sources enabled or just one of them (but we wouldn't know which one). The CCG3PA datasheet stated that CCG3PA can be powered by VDDD or VBUS_IN, so I don't think our multiple power options is an issue. To support all 3 possible combinations of power sources (VDDD + VBUS_IN, VDDD only, or VBUS_IN only), we have to have the internal VBUS regulator enabled.

What I have tried:

I made sure that I don't have pd_hal_disable_vreg(TYPEC_PORT_0_IDX) in my firmware code to ensure that the internal VBUS regulator is ON. This seems to work, as I tried all 3 power combinations. Everything worked.

However, when I reviewed the source code for pd_hal_disable_vreg(), there is a comment that states:

"If system has external VDDD source, internal VBUS regulator shall be turned off."

I don't know if the comment is just a suggestion to save power, or will there be a conflict at an internal power node if I have both VDDD and VBUS_IN with internal VBUS regulator enabled.

Can you please confirm if I have two separate sources for VDDD and VBUS_IN with internal VBUS regulator enabled? Just want to make sure there is no long-term negative effects even though this configuration is working for me.

Thanks,

Jonathan

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1 Solution
ShifangZ_26
Moderator
Moderator
Moderator
10 likes given 250 sign-ins 1000 replies posted

Hi Jonathan,

This is not for suggesting power save. Since VDDD could be input or output (very weak drive capabilities).

If you disable internal 20V regulator, the VDDD shall be input power with range -- 2.7V - 5.5V.

If you enabled the internal regulator, it generates VDDD of 3.3 V for chip operation. BAD case with this condition is: CCG3PA internal regulator enable the regulator, but the external power is not 3.3V.

pastedImage_0.png

Best Regards,

Lisa

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3 Replies
ShifangZ_26
Moderator
Moderator
Moderator
10 likes given 250 sign-ins 1000 replies posted

Hi Jonathan,

This is not for suggesting power save. Since VDDD could be input or output (very weak drive capabilities).

If you disable internal 20V regulator, the VDDD shall be input power with range -- 2.7V - 5.5V.

If you enabled the internal regulator, it generates VDDD of 3.3 V for chip operation. BAD case with this condition is: CCG3PA internal regulator enable the regulator, but the external power is not 3.3V.

pastedImage_0.png

Best Regards,

Lisa

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Thanks Lisa. That is exactly the block diagram that I was looking at.

In my case, my external VDDD power is 3.3V so it matches or closely matches (due to tolerance) the voltage generated by the internal VBUS regulator. Is that a concern?

Thanks,

Jonathan

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Hi Jonathan,

The concerns, whatever of external voltage power, both outputs of regulator short together is not good case. For the design, it shall avoid this case happen. So that  pd_hal_disable_vreg() is recommended.

Best Regards,

Lisa

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