This is not for suggesting power save. Since VDDD could be input or output (very weak drive capabilities).
If you disable internal 20V regulator, the VDDD shall be input power with range -- 2.7V - 5.5V.
If you enabled the internal regulator, it generates VDDD of 3.3 V for chip operation. BAD case with this condition is: CCG3PA internal regulator enable the regulator, but the external power is not 3.3V.
Thanks Lisa. That is exactly the block diagram that I was looking at.
In my case, my external VDDD power is 3.3V so it matches or closely matches (due to tolerance) the voltage generated by the internal VBUS regulator. Is that a concern?
The concerns, whatever of external voltage power, both outputs of regulator short together is not good case. For the design, it shall avoid this case happen. So that pd_hal_disable_vreg() is recommended.