We would like to clarify,
1) What MCU is being used ?
2) What flash or HyperRAM part you are using ?
3) What is this delay to ? The CK# can delay 1ns to the CK, or CK/CK# can delay to the DQ input ?
If you are using Hyperflash, the Semper S26HS family do not need CK# so using that could also be a solution.
MCU: ST Micro STM32L4S5QII @ 1.8v - hyperbus port - single ended clock only
Any Cypress HyperRAM chip ok, prefer 8MB, 105C
Will insert a logic delay of 1ns converting single ended clock to differential clock relative to all other signals.
Propose to use two very fast 1.8v XOR gates on clock (in parallel) to create a pair of complementary clock signals.
TI Gate: SN74AUC2G86YZPR
Is there a better way? Would this work? It would close up eye diagram a bit...
Thanks for the information.
The CK/CK# delay relative to DQ and RWDS impacts to the Input Hold timing (tIH) spec in the HyperRAM. The minimum requirement for tIH in the 1.8V HyperRAM is 0.6ns (https://www.cypress.com/file/183506/download ). In the STM datasheet (https://www.st.com/resource/en/datasheet/stm32l4s5qi.pdf ), the data output hold time, thr/thf(OUT) is specified for some different conditions. If 1ns delay is generated by the XOR, the output hold time should satisfy thr/thf(OUT) - 1ns > 0.6ns. I'm not sure if it is feasible, but it sounds difficult...