3 Replies Latest reply on Aug 15, 2019 12:33 AM by TakahiroK_16

    Using logic to convert to differential clock?

    BeCr_3107286

      Can the hyperbus spec tolerate a 1ns delay in clock? My MCU only has a single ended clock output at 1.8v - I could use a pair of fast XOR gates to convert to psuedo differential. Has this been tried, is there a recommended way to do this? Will be running <100MHz for low power application.

       

      Thanks.