3 Replies Latest reply on Aug 12, 2019 10:29 PM by EktaN_26

    PSoC 3, I/O Configuration at Reset

    NoBu_4396006

      According to the "PSoC 3 and PSoC 5LP Hardware Design Considerations" document, section 4.2 "I/O Pins and Device Reset", "While reset is active, all I/O pins are in the high-impedance analog state." Does this include pins with extra configuration options such as the Op Amp pins and the JTAG pins?

        • 1. Re: PSoC 3, I/O Configuration at Reset
          EktaN_26

          Hello Noah,

           

          In case of  PSoC 3 while reset is active all I/Os (Including pins with reset functionality) are reset to and held in the High Impedance Analog state. . After reset is released, the state can be reprogrammed on a port-by-port basis to pull-down or pull-up. To ensure correct reset operation, the port reset configuration data is stored in special nonvolatile registers. The stored reset data is automatically transferred to the port reset configuration registers at reset release.

           

          Best Regards

          Ekta

          • 2. Re: PSoC 3, I/O Configuration at Reset
            NoBu_4396006

            Hi Ekta,

             

            What do you mean by "including pins with reset functionality"? Does that include the JTAG and Op Amp pins I mentioned?

             

            By the way, I'm asking because I intend to perform some static-bias testing, holding the part in reset mode.

             

            Thanks,

            Noah

            • 3. Re: PSoC 3, I/O Configuration at Reset
              EktaN_26

              Hello Noah,

               

              I made a mistake while typing. I meant pins with other functionality instead of reset functionality. The pins with other functionality includes JTAG and Opamp pins.

               

              Best Regards

              Ekta