1 Reply Latest reply on Aug 22, 2019 2:17 AM by AlakanandaB_86

    SPI communication PSoC 6

    user_349366

      Dear Community,

      for several days I have been trying to write two functions SPI_write and SPI_Read to my program. I used examples and it still doesn't work as it should. As an attachment I send both functions.

      The SPI_Write function should send data to the ADC and not worry about what will come back.

      The SPI_Read function should read data from the ADC. From what I understood, to read the data I must first send the appropriate data to the ADC and then receive a response.

      Please help

      Ɓukasz

       

      int32_t spi_write(struct spi_desc *desc, uint8_t *buffer, uint8_t bytes_number)

      {

        if (desc) {

      // Unused variable - fix compiler warning

      }

       

       

      if (buffer) {

      // Unused variable - fix compiler warning

      }

       

       

      if (bytes_number) {

      // Unused variable - fix compiler warning

         

          uint32_t status = TRANSFER_ERROR;

          cy_en_scb_spi_status_t errorStatus;

          uint8_t statusRxBuf[bytes_number];

          uint32_t masterStatus;       

          /* Timeout 1 sec */

          uint32_t timeOut = 1000UL;

             

         

          /* Initiate SPI Master write and read transaction. */

          errorStatus = Cy_SCB_SPI_Transfer(mSPI_HW, buffer, statusRxBuf, bytes_number, &mSPI_context);

         

          /* If no error wait till master sends data in Tx FIFO */

          if(errorStatus == CY_SCB_SPI_SUCCESS)

          {

             

              /* Wait until master complete read transfer or time out has occured */

              do

              {

                  masterStatus  = Cy_SCB_SPI_GetTransferStatus(mSPI_HW, &mSPI_context);

                  Cy_SysLib_Delay(CY_SCB_WAIT_1_UNIT);

                  timeOut--;

                 

              } while ((0UL != (masterStatus & CY_SCB_SPI_TRANSFER_ACTIVE)) && (timeOut > 0UL));

             

             

              if ((0UL == (MASTER_ERROR_MASK & masterStatus)) &&

                  (bytes_number == Cy_SCB_SPI_GetNumTransfered(mSPI_HW, &mSPI_context)))

              {

                  status = TRANSFER_CMPLT;

       

       

              }

              else

              {

                //  HandleError();

              }

          }

       

       

         

          /* Clear Master status and Tx FIFO status. */

        //  Cy_SCB_SPI_ClearSlaveMasterStatus(mSPI_HW, masterStatus);

        //  Cy_SCB_SPI_ClearTxFifoStatus(mSPI_HW, CY_SCB_SPI_TX_INTR_MASK );

        //  Cy_SCB_SPI_ClearTxFifo(mSPI_HW);

         

             

          /* Clear Rx FIFO status. */

        // Cy_SCB_SPI_ClearRxFifoStatus(mSPI_HW, CY_SCB_SPI_RX_INTR_MASK);

        // Cy_SCB_SPI_ClearRxFifo(mSPI_HW);

       

       

          if (status == TRANSFER_CMPLT)

          {

          Cy_SCB_UART_PutString(UART_PC_HW, "Data written\r\n");

          return SUCCESS;

          }

          else

          {

          return FAILURE;

          }

      }

       

       

       

       

       

       

      /**

      * @brief Read data from SPI.

      * @param desc - The SPI descriptor.

      * @param data - The buffer with thereceived data.

      * @param bytes_number - Number of bytes to read.

      * @return SUCCESS in case of success, FAILURE otherwise.

      */

      int32_t spi_read(struct spi_desc *desc, uint8_t *buffer, uint8_t bytes_number)

      {

        if (desc) {

      // Unused variable - fix compiler warning

      }

       

       

      if (buffer) {

      // Unused variable - fix compiler warning

      }

       

       

      if (bytes_number) {

      // Unused variable - fix compiler warning

         

          uint32_t status = TRANSFER_ERROR;

          cy_en_scb_spi_status_t errorStatus;

          uint8_t RxBuf[bytes_number];

          uint32_t masterStatus;       

          /* Timeout 1 sec */

          uint32_t timeOut = 1000UL;

          char UART[32];

             

         

          /* Initiate SPI Master write and read transaction. */

          errorStatus = Cy_SCB_SPI_Transfer(mSPI_HW, buffer, RxBuf, bytes_number, &mSPI_context);

         

          /* If no error wait till master sends data in Tx FIFO */

          if(errorStatus == CY_SCB_SPI_SUCCESS)

          {

       

       

             

              /* Wait until master complete read transfer or time out has occured */

              do

              {

                  masterStatus  = Cy_SCB_SPI_GetTransferStatus(mSPI_HW, &mSPI_context);

                  Cy_SysLib_Delay(CY_SCB_WAIT_1_UNIT);

                  timeOut--;

                 

              } while ((0UL != (masterStatus & CY_SCB_SPI_TRANSFER_ACTIVE)) && (timeOut > 0UL));

             

             

              if ((0UL == (MASTER_ERROR_MASK & masterStatus)) &&

                  (bytes_number == Cy_SCB_SPI_GetNumTransfered(mSPI_HW, &mSPI_context)))

              {

                  status = TRANSFER_CMPLT;

                 

              }

              else

              {

                 // HandleError();

              }

          }

       

       

       

       

         

          /* Waits till bytes_number bytes is received */

          while (bytes_number != Cy_SCB_SPI_GetNumInRxFifo(mSPI_HW))

          {

               sprintf(UART, "Received bytes: %d\r\n", Cy_SCB_SPI_GetNumInRxFifo(mSPI_HW));

               Cy_SCB_UART_PutString(UART_PC_HW, UART);

               sprintf(UART, "Required bytes: %d\r\n", bytes_number);

               Cy_SCB_UART_PutString(UART_PC_HW, UART);

          }  

         

          /* Read Rx FIFO and clear the status */

      //    Cy_SCB_SPI_ReadArray(mSPI_HW, RxBuf, bytes_number ); 

        //  Cy_SCB_SPI_ClearRxFifoStatus(mSPI_HW, CY_SCB_SPI_RX_INTR_MASK);

      //   Cy_SCB_SPI_ClearRxFifo(mSPI_HW);

          

         

          /* Clear SPI slave and Tx FIFO status */

      //    Cy_SCB_SPI_ClearSlaveMasterStatus(mSPI_HW, Cy_SCB_SPI_GetSlaveMasterStatus(mSPI_HW));

      //   Cy_SCB_SPI_ClearTxFifoStatus(mSPI_HW, CY_SCB_SPI_TX_INTR_MASK );

      //   Cy_SCB_SPI_ClearTxFifo(mSPI_HW);

       

       

          /* Clear Master status and Tx FIFO status. */

        //  Cy_SCB_SPI_ClearSlaveMasterStatus(mSPI_HW, masterStatus);

       

       

       

       

         

          /* Clear Rx FIFO status. */

      //    Cy_SCB_SPI_ClearRxFifoStatus(mSPI_HW, CY_SCB_SPI_RX_INTR_MASK);

       

       

       

       

          if (status == TRANSFER_CMPLT)

          {

          Cy_SCB_UART_PutString(UART_PC_HW, "Data written\r\n");

         

               sprintf(UART, "Value of RxBuffer: %d %d %d %d %d %d %d %d\r\n", RxBuf[0], RxBuf[1], RxBuf[2], RxBuf[3], RxBuf[4], RxBuf[5], RxBuf[6], RxBuf[7]);

               Cy_SCB_UART_PutString(UART_PC_HW, UART);

            

          CyDelay(5000);

         

          return SUCCESS;

          }

          else

          {

          Cy_SCB_UART_PutString(UART_PC_HW, "cos nie tak");

          return FAILURE;

          }

       

       

      }