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Hello,
I am testing the CE210291_CapSense_P4_One_Button example using a CY8CKIT-145-40XX PSoC® 4000S CapSense Prototyping Kit.
I have changed the example I2C pins to P1[0] and P1[1] for compatibility and cap sensing on P1[5] after removing the R47 touch button series resistance.
CapSense scan is configured at 8bit, 3000KHz sense clock frequency
System->Debug Select->GPIO is selected to disable the debugger.
I measured the current consumption on J3 after removing R22 0-ohm resistor, in Slow scan mode is 270uA and in fast scan mode is 280uA while expecting less than 6uA consumption in slow scan mode.
Is there some peripheral to be disable or some HW component to be removed from the evaluation board?
Thank you,
Alessio Balbo
Solved! Go to Solution.
- Labels:
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ispn:40040:1:0
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l1:314:1:0
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Hi alba_4340081
In the System tab of Design Wide Resources, please set the VDDA and VDDD voltages to 5V. This would set the reference voltages correctly and give you the low current consumption.
Thanks and regards
Harigovind
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You need to disable debugging capabilities by setting the pins to GPIO mode in "System" view of dwr-file.
Bob
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JoMe_264151 wrote:
You need to disable debugging capabilities by setting the pins to GPIO mode in "System" view of dwr-file.
Bob
I already set Debug Select->GPIO in the system view. If instead I select "SWD" consumption rise up to 1.5mA
Alessio
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Hi alba_4340081
In the System tab of Design Wide Resources, please set the VDDA and VDDD voltages to 5V. This would set the reference voltages correctly and give you the low current consumption.
Thanks and regards
Harigovind