3 Replies Latest reply on Aug 4, 2019 9:49 PM by YatheeshK_36

    Can JTAG only mode of FPGA  drive slave fifo mode of CYUSB FX2LP?

    MSSa_1300736

      Hi All,

      I want to collect data from 12 bit ADC and sent it to PC through CYUSB FX2LP usbcontroller with help of 7series FPGA XC7S15. In this application, I'll going to use FX2LP in slave FIFO mode (CYUSB as Slave). So all slave configuration is USB side.

      Is it possible to operate FPGA in JTAG only mode or I have to use FPGA in MASTER SPI mode and generate CCLK from FPGA to CYUSB?

      I have refered documents of both xilinx fpga and Cypress's CYUSB FX2LP's application note : AN61345. But I am not clear that for SLAVE FIFO mode of CYUSB; what must be FPGA's mode to be configured? For example, Can I connect SRCC or MRCC clocks from FPGA to IFCLK of CYUSB to make it operate in slave fifo mode or is it compusory to generate it from CCLK of FPGA?

      https://www.cypress.com/file/44551/download

      Thanks and Regards