To get higher frequency range you can use DDS24 or DDS32 community components instead of PWM
which provide 24-bit and 32-bit frequency range accordingly. As a bonus, unlike the PWM, with DDS you can directly set any frequency.
1 of 1 people found this helpful
Moto and \odissey1 definitely have valid suggestions.
I'll provide another one for academic purposes.
As the clock to your PWM you are using the BUS_CLK directly. This clock is the most efficient for allocating clock resources on the PSoC.
However if you change to using either "Auto" or "MASTER_CLK" instead, you can use a digital clock resource which has a 16 bit divider available for control of the input clock to your 16-bit PWM. Together, you get a combined 32bits of division available to your application.
You already know how to change the PWM period. To change the incoming clock divider just use:
Clock_SetDivider(uint16 clkDivider) where clkDivider is the desired divider + 1.
I'll provide yet another one.
If you want to get a high division ratio divider, It is easy to cascade multiple dividers.
Because the propagation delay from the "en" input to "div" output cannot be ignored, the "div" output is synchronized with the "clk" input.
If you want a 50% duty clock output, please use a TFF at the last stage.
This prescaler implementation is a part of my frequency counter. Please refer following repository for the project.
You can also see a BLOG article in Japanese.
Thank you for all suggestion and recommendation from all of you, it's helpful and I learned a lot.