3 Replies Latest reply on Aug 27, 2019 5:30 AM by VasanthR_91

    ADC Channels and Errata questions regarding CY8C62xA data sheet?

    WeGa_288606

      Hi,

       

      We are using a CY8C62xA in 128-TQFP per "Document Number: 002-23185 Rev. *G". We have several questions that we need Cypress support with.

       

      [ADC Channels and ADC Errata]

      1. Page 42, Table 15, suggests SAR ADC MAX number of SE channels is 16. We are designing using PN CY8C624AAZI. ModusToolbox configured with said PN allows Programmable Analog 12-bit SAR ADC Peripheral to be configured for 16 SE channels and shows/enables channels 0-15 options but only P10[0]-P10[7] are selectable within each channel. Where are the other 8 channels? This would also apply to differential mode similarly... i.e. 16 channels needed for 8 channel differential....where are the remaining 8?
      2. Page 69, Errata Section with table title "3. Switching noise can cause ADC errors due to voltage reference noise." Suggests that: "......including the SAR ADC, is connected to Ports 9 and 10." are the missing channels actually on Port 9? Not yet implemented in ModusToolbox?
      3. Please help me understand the use of your term "Switching". Are we strictly speaking digital switching or what of the switching inherent to ADC sampling? For example: If we assume that all 16 ADC channels entirely exist on ports 9 and 10 such that we use ports 9 and 10 strictly for ADC with all channels "simultaneously sampling" will we see a 4 count LSB error or a 12 count LSB error on ADC? Or otherwise if we have only 8 channels on port 10 all used as simultaneous ADC are we looking at 4 count LSB or 12 count LSB? etc..??

       

      Please advise.

       

      ADC.jpg

        • 1. Re: ADC Channels and Errata questions regarding CY8C62xA data sheet?
          VasanthR_91

          Hello Wess,

           

          1) We are checking internally about the connectivity issues in Modus. Meanwhile PSoC 6 does not have output connectivity to 16 GPIOs. It supports 16 channels in the hardware. The port 10 pins which can be directly connected to the ADC through SARMUX, 2 inputs through AMUX BUS(AMUX Bus A and AMUX Bus B), output of the opamps, the die temperate input are the connections possible for the  ADC. The channel maximum is set to 16 because that is the maximum channel count that the hardware supports. The way to fully utilize these 16 channels is to replicate one input on multiple channels. This is useful because each channel corresponds to a dedicated result register in the SARSEQ so replicating a channel allows multiple results to be stored before the CPU needs to awaken and handle the results. For example, consider a design with the maximum 12 sensors, of which 4 need to be sampled twice as frequently as the other eight. You could implement this entirely in hardware by assigning each of the four "fast" sensors to two channels and assigning each of the remaining eight "slow" sensors to one channel.

           

          2) Port 9 pins are recommended to be used as ADC input after port 10 pins. Other port pins can be also connected but with the restrictions as said in errata. Please check hardware design considerations application note. Regarding the Modus Toolbox part I will update you.

           

          3)Switching due to SPI/CLK can affect the results. So it is advisable to use different ports or not use such signals during ADC conversion in the design.

           

          Best Regards,
          Vasanth

          2 of 2 people found this helpful
          • 2. Re: ADC Channels and Errata questions regarding CY8C62xA data sheet?
            WeGa_288606

            Hi Vasanth,

             

            Thank you for your time and response. I understand the nature of AMUX but I guess what I am saying is that only port 10 pins seem to be an option and for complete routing of 16 channels we need 8 more pins somewhere and somehow in ModusToolbox. I am also suggesting that the language of the errata seems to imply (or I am incorrectly inferring) that the analog "stuff" is only available/connected/route-able to ports 9 and 10.

             

            "The Programmable Analog Sub-System (PASS), including the SAR ADC, is connected to Ports 9 and 10."

             

            Currently we have three sensors on SPI/SCB/Port 9 pins that we plan on using SPI/CLK as fast as we can. In light of the errata I am considering a redesign now and I am trying to asses where to move  things around to but I cannot do that until I know where all my Analog A2D pins are as we plan on using all 16 channels in differential mode. It is a bind for us because we are actually using all 128 pins of the device as well as all SCBs. So this analog stuff really took a punch at us.

             

            This is why I am trying to understand the errata comments. Digital switching from clocks vs switching from SAR sequencing or from SPI data lines etc...? A lot of different kinds of "switching" could exist on port 9 and port 10 and I am trying to pick the worse of all evils in this case....

             

            Switching in Ports 9 and 10 is restricted to 1 MHz (no more than 2 outputs) with

            slow slew rate setting and, in this case, the ADC error may be up to 12 counts

             

            Please let us know about ModosuToolbox routing first chance you get and thank you again for the support.

             

            Cheers,

            Wess 

            • 3. Re: ADC Channels and Errata questions regarding CY8C62xA data sheet?
              VasanthR_91

              Hello Wess,

               

              There was an inaccuracy in the previous response. Correcting the point number 3, the switching due to SPI/CLK can affect the results. So it is advisable to use different ports or not use such signals during ADC conversion in the design.

               

              Regarding your question of inability to use other ports for Modus, this will be resolved in the next version of Modus which is going to be released soon.

               

              Best Regards,
              Vasanth