1 of 1 people found this helpful
Please refer following document.
PSoC 5LP Architecture TRM, Document No. 001-78426
There are two groups of clock dividers, Digital and Analog.
When a Clock is put on the PSoC Creator's schematic,
the clock domain is selected from DIGITAL and ANALOG
Once the clock is attached to the Counter component,
the clock domain is fixed to DIGITAL.
If you didn't see any error on PSoC Creator, the clock can be used as the FF-type Counter clock.
your comments have cleared up my problem
i wasn't using the clocks correctly