About data retention of SRAM when software watchdog reset occurs

[SuSh_1535366]

Hello,

When a software watchdog reset (SWDGR) occurs, if DSRAMR is set correctly, is the data in SRAM2 retained?

At this time, the data in SRAM0/1 can not be retained, is this right?

Regards,

Shimamura

[Takashi_M · Accepted solution]

You may mix up with the software watchdog reset and Deep Standby mode.

Even though the software watchdog reset happens, SRAM0/1/2 can be retained with values just before the reset.

In Deep Standby mode, the power supply for SRAM0/1/2 is turned off inside device. that mean that SRAM0/1/2 are not retained in this mode.

Note that if DSRAMR is configured as the contents of SRAM2 is retained, SRAM2 is retained even in Deep Standby mode.

[SuSh_1535366]

Hello TakashiM_61,

Thank you for your reply!