6 Replies Latest reply on Jul 21, 2019 11:34 PM by JeHu_3414236

    PSoC 62 VDDIO0 voltage

    JeHu_3414236

      I am connecting VDDIO0 to 2.5V for e-fuse programming while the rest of the VDD voltages are 1.8V or 3.3V.  When the chip is powered off, all voltages are 0V but VDDIO0 will remain at 2.5V in some cases.  Will this design have any problems?