1 Reply Latest reply on Jul 9, 2019 11:03 AM by BoTa_264741

    PSoC 5LP clock frequency detection is unstable

    TaYu_4314136

      *I posted a question similar to this the other day but I created as a new thread because I thought that this question didn't related UDP directly.

       

      I want to capture 48kHz(6.144 MHz) S/PDIF audio signals by PSoC 5LP(CY8CKIT-059). So I created a circuit to synchronize a signal using 12.288Mhz crystal. It should be able to obtain correct data every 2 bits at least theoretically because the base clock is just twice as fast as an audio signal.

       

      12clk.png

       

      top.png

      (*Pin_2 is for verification by logic analyzer)

      12clkdlg.png

       

      This is the result received from my custom component. (1 is high / 0 is low on every clock)

       

      122_2.png

       

      Looking at this, PSoC often seems to skip(not out of position) clock edges. This was not improved by changing a clock source from XTAL to Digital Input(with a crystal oscillator).

       

      This is a full project(OneDrive). There are many options such as "High impedance digital / Strong drive" for pin assignment, so it is difficult for me to find the best option. Please tell me how to create a circuit or settings to receive an accurately clock.

        • 1. Re: PSoC 5LP clock frequency detection is unstable
          BoTa_264741

          TaYu,

          I experimented with digital input as PLL clock, and result is that PSoC5' PLL doesn't lock to SPDIF signal. It captures the frequency, but not the phase (it is loose). This is due to high current setting of the PLL pump (2uA default), which causes PLL to follow input signal on ~10us time scale (too fast). Unfortunately, SPDIF signal is too jittery, it has some short and some long periods, and PSoC5's PLL is not able to lock it's phase to SPDIF input. When current pump lowered to 1uA, the PLL trace clears a little, but not enough to lock the phase. Unfortunately, 1uA is the lowest setting for PLL. Bottom line - don't use external SPDIF signal as PLL source in Clock settings page, as this won't help.

           

          External 4046 PLL will work for sure extracting the SPDIF carrier clock, but I believe that using few passive hardware components, PSoC5 can be locked to SPDIF signal without 4046, see example here:

          Simple FM audio transmitter using PSoC5

          /odissey1