I experimented with digital input as PLL clock, and result is that PSoC5' PLL doesn't lock to SPDIF signal. It captures the frequency, but not the phase (it is loose). This is due to high current setting of the PLL pump (2uA default), which causes PLL to follow input signal on ~10us time scale (too fast). Unfortunately, SPDIF signal is too jittery, it has some short and some long periods, and PSoC5's PLL is not able to lock it's phase to SPDIF input. When current pump lowered to 1uA, the PLL trace clears a little, but not enough to lock the phase. Unfortunately, 1uA is the lowest setting for PLL. Bottom line - don't use external SPDIF signal as PLL source in Clock settings page, as this won't help.
External 4046 PLL will work for sure extracting the SPDIF carrier clock, but I believe that using few passive hardware components, PSoC5 can be locked to SPDIF signal without 4046, see example here: