1 of 1 people found this helpful
Yes. As you said, there is back-power provided due to say LED's, I2C pull-up lines. Here, the voltage domains in the PSoC6 chip are powered if the voltage in the PSoC6 pin is greater than that of the domain. As you removed R28, the Vtarg powers the chip through either LED or the I2C with the resistors in these lines providing a drop in voltage at P6_VDD.
The idea here is that the LED current consumption or current provided due to I2C pull-up should not come into picture during current measurement.
The current consumed only by the PSoC 6 chip will be shown by the header J3.
PSoC 6 programs even if the VDDIO lines in the SWD port and the VDDD voltage are as low as 1.8V.
I don't think it is a concern or that it has detrimental effect to the module. If there is enough current to power the internal circuitry, the programming will take place or else it won't.