2 Replies Latest reply on Jul 5, 2019 8:54 AM by ChRO_4339966

    FIFO Slave / GPIF interface clock direction




      I am considering using FX3 as a bridge between USB and FPGA.

      It would be mainly used to pass data from USB to application via FX3 at maximum BW (low traffic in other direction).

      My project is at board design level.


      Looking at documentation and tools, it looks like 32-bit synchronous FIFO Slavemode  @ 100 MHz would be OK for me.

      All implementations I found describe an interface where FPGA is master of the clock.


      I would like to keep the ability to have FX3 driving this clock (still using maximum frequency, ie 100 MHz).

      Example design provided in GPIF designer does not allow to modify clock direction.


      Is there a simple solution to do so ? Or should I redesign everything (GPIF interface definition, state machine, FX3 firmware...)

      Are there side effects using such a configuration ?


      Thanks for your help