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Hello,
Because my application is requiring a lot of DMA channels, I'd like to use as much as possible different TDs rather than separated channels triggered buy TERMOUT lines.
What I have to do: in order to transfer graphical data to a TFT display, I have to set a write strobe signal (WR) to zero, place the data on the data bus (D0-7) and then write WR back to 1.
My intention was to use one DMA channel, with 3 TDs in order to synchronize the 3 operation in one sequence. Unfortunately, the incoming graphical data is retrieved from a flash rom via SPI (PERIPH) and goes to an 8bits control register (PERIPH) but the setting of the WR signal (via control register) would need a transfer from SRAM to PERIPH which cannot be done with the same DMA channel.
I thought about using 2 different Status register on which I would simply connect, for one a logic 1, and for the other a logic 0: that way I could transfer from the status register (PERIPH) to the control register (PERIPH) the correct value. This doesn't work because the optimization will simply not implement the status register connected to a logical 0 (I could do it by setting unused bits to 1... but it doesn't feel very elegant).
I'm probably doing things completely wrong… and hope someone could tell me where
Thanks a lot for your help.
Serge
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I created a component "PureRegister"
This component implements a datapath.
The registers A0 and A1 can be read and write through the API functions.
A DMA capability file is contained for DMA wizard.
I have tested read/write function with CPU but not tested DMA.
Please import the component from the project or the component archive.
Regards,
Noriaki
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I recommend to use a combination of a DMA and a UDB-based custom component.
There is an example project using a TFT display connected with an 8-bit parallel bus.
The example project CE222221 – PSoC 6 MCU Voice Recorder is a project for the PSoC 6 but the custom component part will be reusable.
Because this TFT interface is not supporting DMA. So, I have revised the component to support DMA. Please refer following repository for revised projects.
The project "Driver10" is supporting DMA transfer.
Regards,
Noriaki
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Thank you very much Noriaki san for your time and effort .
Your project is very interesting but, unfortunately I don't have the opportunity to modify my hardware architecture or components and therefore, my question still stands:
I would like to know how to efficiently create 2 fixed value in PERIPH address range in order to use 1 DMA channel (PERIPH -> PERIPH) with multiple TDs.
As you might have understood by now, I'm lacking the knowledge and experience in PSoC development: please accept my apologies if this is a trivial question .
Thanks
Serge
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I created a component "PureRegister"
This component implements a datapath.
The registers A0 and A1 can be read and write through the API functions.
A DMA capability file is contained for DMA wizard.
I have tested read/write function with CPU but not tested DMA.
Please import the component from the project or the component archive.
Regards,
Noriaki
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Thanks a lot, this is what I needed
All the best
Serge