4 Replies Latest reply on Sep 11, 2019 12:18 AM by user_4064026

    HyperBus Memory Controller IP does not response write transaction during write response(BVALID remains deasserted)

    user_4064026

      I implemented your HyperBus Memory Controller IP on several
      technology. Now I am trying it on different technology. I have a issue and I
      want to learn cause of problem. I configured the HyperBus Memory Controller IP
      as compatible with HyperRAM over AXI register interface. There was not any
      error for both read and write operation to IP registers. However IP does not
      assert BVALID write response channel signal When I try to write to HyperRam
      over AXI memory interface.Can you help me about this issue?.What could be cause
      of this issue?