Could you make sure the following items?
1) AXIm_ACLK is supplied
2) If you are using AXI4, AXIm_WID is fixed to 0
I checked AXIm_ACLK and It is supplied. Also AXIm_ACLK and AXIr_CLK are same.There is not any problem AXI Control Register side.
I am using AXI4 and I checked AXIm_WID and It is fixed to 0.
Since apologies for the delay in our response.
1. Could you please let us know the hardware that you use (FPGA or Evaluation boards)?
2. Did you receive any example VIVADO projects from Cypress for Xilinx FPGA?
Thanks and Regards,
I solved the problem thanks for your responses.The problem was IP initialization during reset procedure.