4 Replies Latest reply on Jul 1, 2019 10:52 PM by jumac_686261

    ZLP in U3V protocol

    jumac_686261

      Hi everyone.

      Could someone please help me, please.

       

      I'm now designing data transfer from FPGA to PC via FX3 using synchronized interface.

      The FPGA works as:

      1. Assert SLCS/SLWR first.

      2. Send 52 bytes data (Leader) with PCLK.

      3. Then deassert SLCS/SLWR once.

      4. Assert SLCS/SLWR again.

      5. Assert PKTEND (with PCLK)

      6. Deassert PKTEND/SLCS/SLWR.

      7. After this, video data will be transferred with same sequence.

      My GPIO is configured as shown in GPIOstatemachine.jpg.

       

      The PC receives Leader correctly, this is good.

      But the problem is, it seems the ZLP arrives after the Leader packet.

      Is it correct always ZLP issued ?

      Could you please let me know my GPIO design has any problems.

       

      Thank you,

        • 1. Re: ZLP in U3V protocol
          KandlaguntaR_36

          Hello,

           

          It looks like you are driving the flags such way- ZLP is being sent. You have to send a Short packet.

           

          Refer An65974 for this implementation.

          https://www.cypress.com/documentation/application-notes/an65974-designing-ez-usb-fx3-slave-fifo-interface

           

          Short Packet: A short packet can be committed to the USB host by using the PKTEND# signal. The external

          device/processor should be designed to assert the PKTEND# along with the last word of data and SLWR# pulse

          corresponding to the last word. The FIFOADDR lines must be held constant during the PKTEND# assertion. On

          assertion of PKTEND# with SLWR#, the GPIF II state machine interprets the packet to be a short packet and commits

          it to the USB interface. If the protocol does not require any short packets to be transferred, the PKTEND# signal may

          be pulled high

           

          Zero-Length Packet: The external device/processor can signal a zero-length packet (ZLP) by asserting PKTEND#,

          without asserting SLWR#. SLCS# and address must be driven, as shown in Figure 5.

           

           

           

          as shown in Figure 5.

          • 2. Re: ZLP in U3V protocol
            jumac_686261

            KandlaguntaR_36 san,

            Thank you for your reply.

             

            I understood short packet and zero-length packet mechanism, thank you.

             

            As I have mentioned in my first question, after writing 52 bytes Leader data, my FPGA asserts PKTEND# with asserting SLWR#/SLCS#

            to send this short packet.

            In this sequence my DMA callback function is called twice, once for 52 byte data (leader) and once for zero-length buffer (ZLP).

            So my firmware code discard buffer when DMA buffer size is zero (to cut ZLP).

            The reason why discarding ZLP is that the U3V protocol driver in a PC side sends CLEAR FEATURE when receiving the ZLP.

            It should be a payload data just receiving after the Leader packet.

            I think the U3V protocol does not require ZLP because the payload size is quite clear at both ends.

             

            One more question for ZLP.

            Is the ZLP rule you mentioned above, asserting PKTEND# without asserting SLWR#, hard coded in the FX3 ?

            Or is it possible to manage by changing the state machine code using GPIF II designer ?

             

            Anyway I will check the PKTEND#/SLWR#/SLCS# signals again.

             

            Best Regards,

            • 3. Re: ZLP in U3V protocol
              KandlaguntaR_36

              Hello,

               

              Is the ZLP rule you mentioned above, asserting PKTEND# without asserting SLWR#, hard coded in the FX3 ?

              Or is it possible to manage by changing the state machine code using GPIF II designer ?

               

              >> It is configured in the GPIF II state machine.

               

              I recommend you to assert the PKTEND# along with the last word of leader and SLWR# pulse corresponding to the last word.

              This will send only leader to USB host.

               

              Regrads,

              Sridhar

              • 4. Re: ZLP in U3V protocol
                jumac_686261

                Greetings,

                 

                Thank you for your quickly response.

                I will try to adjust PKTEND# timing.

                Once more, Thank you!