13 Replies Latest reply on Jul 25, 2019 12:25 AM by SrinathS_16

    FX3 SPI INTERFACE

    gean_3054931

      Hello,

      SPI interface (SPI_SCK,SPI_SSN,SPI_MISO,SPI_MOSI) in fx3 works only for booting(4 bit wire interface with spi flash).I cant use these (with another CHIPSELECT )spi controller for other slave (example zynq as slave controller).

      if i do this interface,fx3 booting is going to fail.

      what is the reason?

       

      Thank you.

        • 1. Re: FX3 SPI INTERFACE
          SrinathS_16

          Hello,

           

          - Please explain how is the other slave device connected to the FX3 master. Is a GPIO pin on FX3 being used as Slave Select pin for the other slave?

          - Do you see any activity on the SPI lines upon booting? Are the initial 'CY' signature bytes being transmitted successfully?

           

          Best regards,

          Srinath S

          • 2. Re: FX3 SPI INTERFACE
            gean_3054931

            Hello,

            GPIO[47] is other slave select.

            1)I can see programming of spi flash is sucessfull but after reset ,fx3 comes up with bootloader device with zynq spi interface.

            2)FX3 booting is succesfull without zynq spi interface.(means there is no another slave for fx3 other than spi flash device).

             

            thank you

            • 3. Re: FX3 SPI INTERFACE
              NoriakiT_91

              If you want to use two SPI slave devices with FX3. Two SSN lines must be controlled by your firmware.

              The UsbSpiRegMode project example has the firmware controlled SSN line.

               

                  /* Start the SPI master block. Run the SPI clock at 8MHz
                   * and configure the word length to 8 bits. Also configure
                   * the slave select using FW. */
                  CyU3PMemSet ((uint8_t *)&spiConfig, 0, sizeof(spiConfig));
                  spiConfig.isLsbFirst = CyFalse;
                  spiConfig.cpol       = CyTrue;
                  spiConfig.ssnPol     = CyFalse;
                  spiConfig.cpha       = CyTrue;
                  spiConfig.leadTime   = CY_U3P_SPI_SSN_LAG_LEAD_HALF_CLK;
                  spiConfig.lagTime    = CY_U3P_SPI_SSN_LAG_LEAD_HALF_CLK;
                  spiConfig.ssnCtrl    = CY_U3P_SPI_SSN_CTRL_FW;
                  spiConfig.clock      = 8000000;
                  spiConfig.wordLen    = 8;
              
              
                  status = CyU3PSpiSetConfig (&spiConfig, NULL);
              

               

              At the SPI configuration in CyFxSpInit() function the ssnCtrl field is set to SSN_CTRL_FW to control the SSN with the firmware.

               

                          CyU3PSpiSetSsnLine (CyFalse);
                          status = CyU3PSpiTransmitWords (location, 4);
                          if (status != CY_U3P_SUCCESS)
                          {
                              CyU3PDebugPrint (2, "SPI READ command failed\r\n");
                              CyU3PSpiSetSsnLine (CyTrue);
                              return status;
                          }
              
                          status = CyU3PSpiReceiveWords (buffer, glSpiPageSize);
                          if (status != CY_U3P_SUCCESS)
                          {
                              CyU3PSpiSetSsnLine (CyTrue);
                              return status;
                          }
              
                          CyU3PSpiSetSsnLine (CyTrue);
              

               

              Of course you must assert and negate the SSN line with the CyU3PSpiSetSSnLine() function or a GPIO control function for a second SPI slave device..

               

              Regards,

              Noriaki

              • 4. Re: FX3 SPI INTERFACE
                gean_3054931

                Hi,

                I am facing FX3 booting issue.Even bulkloop example is not getting booted with zynq spi interface signals.

                bulkloop example succesfully booted without zynq spi interface signals.

                 

                why this is happening even with basic bulkloop example.i have not used any software control on  spi communication with zynq.

                 

                thank you.

                • 5. Re: FX3 SPI INTERFACE
                  NoriakiT_91

                  I recognized that your problem is you cannot boot from an emulated EEPROM implemented in zynq.  Please let me confirm my understanding is correct.

                   

                  Please refer "https://www.cypress.com/AN70707 " There is a SPI configuration figure for the SPI boot as follows.

                   

                  GS004179.png

                   

                  If the pull-up and pull-down configurations are incorrect, the SPI boot will fail.  Please ensure the level of these signals at FX3's reset timing.

                   

                  Regards,

                  Noriaki

                  • 6. Re: FX3 SPI INTERFACE
                    gean_3054931

                    Hello,

                    hardware for spi boot is proper.Same as fx3 dvk along with resistor values.

                    fx3 is booted succesfully with bulkloop example and also other examples also.

                    1)if fx3 is spi master and spi flash is slave,booting is succesfull.

                    2)if fx3 is spi master and two slave devices,one is spi flash and another one is zynq as slave.

                    for the 2 point,FX3 shares same MISO,MOSI  and CLOCK line,If FX3 shares the hardware lines to zynq,booting is failed.

                     

                    booting fail->

                    for this,its showing "programming of spi flash is succesfull" but after reset,its comesup with bootloader device.

                     

                    regards,

                    geetha.

                    • 7. Re: FX3 SPI INTERFACE
                      NoriakiT_91

                      Which signal is connected to the zynq's SS?  GPIO[47] ?

                      Please ensure the zynq's SS is properly pull-up during the BOOT sequence.

                      When synq's SS is negated (HIGH),  please ensure the MISO output of zynq is Hi-Z.

                       

                      If the BOOT failed when zynq connected, there is any problem in zynq.

                       

                      Regards,

                      Noriaki

                      • 8. Re: FX3 SPI INTERFACE
                        gean_3054931

                        Hello ,

                        please look at schematic attached to this thread.

                        Please ensure the zynq's SS is properly pull-up during the BOOT sequence.

                        CS_ZYNQ is pulled-up.

                        • 9. Re: FX3 SPI INTERFACE
                          NoriakiT_91

                          I understand.

                          Please remove the pull-up resistors at MISO and MOSI, these are R257 and R264 as the AN70707 said.

                          GS004277.png

                          This is a limitation when SPI Flash is used for boot.

                           

                          Regards,

                          Noriaki.

                          • 10. Re: FX3 SPI INTERFACE
                            gean_3054931

                            Hello,

                            Resistor R257 and  R264  were removed in our hardware setup.

                            but problem was same.

                             

                            thanks

                            geetha.

                            • 11. Re: FX3 SPI INTERFACE
                              gean_3054931

                              Hello Noriaki,

                              anything need to change in our hardware or software?

                               

                               

                              thanks,

                              geetha

                              • 12. Re: FX3 SPI INTERFACE
                                NoriakiT_91

                                I cannot find any problem in the area of your schematic image.

                                Please confirm if the ZYNQ does not drive the SPI bus signals SCK, MOSI, and MISO out of the RESET.

                                The current flow can be detected when the resistors R240, R241, and R243 are exchanged with 100 ohms resistors and observe the voltage drop at each resistor.

                                 

                                Regards,

                                Noriaki

                                • 13. Re: FX3 SPI INTERFACE
                                  SrinathS_16

                                  Hello Geetha,

                                   

                                  Please probe the SPI lines and check if there is any initial activity on these lines during the boot-up. Share the captures.

                                   

                                  EDIT: FX3 samples the state of MISO line to identify the address cycles used by the flash device. Hence, it is essential that the MISO line is not left floating or puled HIGH during this address cycle identification. It is recommended to use a pull-down resistor on the MISO line.

                                   

                                  Best regards,
                                  Srinath S