8 Replies Latest reply on Jul 3, 2019 6:38 PM by KeTa_1341526

    About IO state of SWD

    KeTa_1341526

      Hello,

       

      I want to know the status of each SWD port in the setting that enables SWD port in PSoC4.

      The attached image was considered based on the following information.

       

      - I/O State on Power Up

        PSoC® Analog Coprocessor Architecture Technical Reference Manual (TRM) [Document No. 002-10404 Rev. *C January 9, 2019]

      https://www.cypress.com/file/273431/download

        P.72 [7.6 I/O State on Power Up]

      - Acquire the Chip After Hard Reset

        Programming Specifications [Document No. 002-22326 Rev. *B]

        https://www.cypress.com/file/409521/download

        P.43 [4.3 Step 1A – Acquire the Chip After Hard Reset]

      - Internal Register

      Re: About processing of debug pins (SWDCK, SWDIO)

       

       

      I want to know about the following things.

       

      Q1. Pin status with nothing(Host etc.) connected to SWD port.

             If Input Buffer is enabled on the SWD port, pull-up / down of the input is necessary to prevent IO destruction.

             However, although it confirmed on the evaluation board, it was in High-Z state.

             As my guess, isn't the Input buffer in an invalid state?

             (Because of that, it looks as High-Z state)

       

      Q2. If the device is reset in the Reset cycle Mode / Power cycle mode, does SWD Port enable the input buffer and internal pull-up/down?

       

      Q3. If the Host does not issue a Line Reset signal to the SWD port, does the SWD port disable the input buffer and internal pull-up/down?

             And does the state of IO become High-Z state?

       

      Best Regards,

      Kenji Takahashi

        • 1. Re: About IO state of SWD
          TakashiM_61

          We have to apologize for late response.

           

          Although still some double checks are needed,

          For Q1, when nothing is connected to SWD port, these pins are High-Impedance Digital mode. So input buffer is enabled.

          For Q2, During power up, the pins for SWD is enabled as SWD lines. So, the answer is “YES”.

          Internal buffer is enabled, and SWDIO have internal pull-up and SWDCK have an internal pull-down.

          The reference is the PSoC® Analog Coprocessor Architecture Technical Reference Manual (TRM).

          https://www.cypress.com/file/273431/download

           

          For Q3, the answer is “NO”.

           

          Once double check is done, will update this thread as soon as possible.

          • 2. Re: About IO state of SWD
            TakashiM_61

            The double check was done.

            • 3. Re: About IO state of SWD
              KeTa_1341526

              Takashi-san,

               

              Thank you for your reply.

              But I am not convinced about the answer to Q1.

              If input buffer is enabled in High-Impedance Digital mode, will it not be possible to destroy the input buffer if a pull up / down resistor is not connected externally?

              I am concerned about the damage to the input buffer by the through current.

               

              There is no pullup / down instruction in the Hardware guide Application note.

              Also, there is no pullup / down for SWD on Cypress Evaluation Kit.

               

              Also, in the ARM documentation, external Pullup is conventionally recommended.

              Please explain why there is no need for external pullup in PSoC.

               

              I am concerned about the damage to the input buffer by the through current.

               

              Best regards,

              Kenji Takahashi

              • 4. Re: About IO state of SWD
                TakashiM_61

                There is a protection internally for each pin including SWD.

                And, any current in specification respecting to latch-up current is safe.

                Please check latch-up current in datasheet.

                https://japan.cypress.com/documentation/datasheets/psoc-analog-coprocessor-cy8c4axx-family-datasheet

                • 5. Re: About IO state of SWD
                  KeTa_1341526

                  Takashi-san,

                   

                  From the data sheet, the latch-up current seems to be ±140mA.

                  In the case of through current, is it better to consider this ±140mA or less?

                  However, in the external noise situation, is it not necessary to use an external pullup/down to limit the current value to within ±140mA?

                   

                  And,

                  Please let me check again.

                  If the SWD port is not connected to Host, is it in High-Impedance Digital mode?

                  Is this port in an unused GPIO state and High-Impedance Analog mode until the SWD is connected?

                  It refers to the following statement.

                   

                  PSoC® Analog Coprocessor Architecture Technical Reference Manual (TRM)

                  https://www.cypress.com/file/273431/download

                  P.61

                  ■ High-Impedance Analog

                  High-impedance analog mode is the default reset state; both output driver and digital input buffer are turned off. This state prevents an external voltage from causing a current to flow into the digital input buffer. This drive mode is recommended for pins that are floating or that support an analog voltage.

                   

                  Best regards,

                  Kenji Takahashi

                  • 6. Re: About IO state of SWD
                    KeTa_1341526

                    Takashi-san,

                     

                    It is my understanding based on your answer.

                     

                    1. Set Debug Select to "GPIO" in the cydwr file

                        - Programming Only

                        - (SWD host connected)

                           During power on or reset, Line reset is issued from Host and SWD port of Device(PSoC) enables SWD circuit.

                           During this time, SWDIO have internal pull-up and SWDCK have an internal pull-down.

                           I/O status is Hi-Z Digital Mode.

                        - (SWD host un-connected)

                            Become GPIO after power on.

                            GPIO status is Hi-Z Analog Mode.

                            In this mode, output driver and digital input buffer are turned off.

                            Therefore, there is no need for external pull-up / pull-down.

                     

                    2. Set Debug Select to "SWD" in the cydwr file

                        - Run-time debug and Programming

                       - (SWD host connected)

                           During power on or reset, Line reset is issued from Host and SWD port of Device(PSoC) enables SWD circuit.

                           During this time, SWDIO have internal pull-up and SWDCK have an internal pull-down.

                           Pin status is Hi-Z Digital Mode.

                        - (SWD host un-connected)

                           I/O status after power on is Hi-Z Digital Mode.

                           Therefore, external pull-up / pull-down is required. (recommended 10k-ohm pull-down).

                     

                    Is my recognition correct?

                     

                    Best regards,

                    Kenji Takahashi

                    • 7. Re: About IO state of SWD
                      TakashiM_61

                      1. Set Debug Select to "GPIO" in the cydwr file

                      The pin state is Hi-Z Analog state, and it is changed during flashing protocol/procedure.

                       

                      2. Almost correct. if you would like to consider power consumption, it wold be good to put external pull-up/down registers.

                      And regarding the value of register, please mount the applicable/suitable registers depending on your board design/system.

                       

                      • 8. Re: About IO state of SWD
                        KeTa_1341526

                        Thank you for your reply.

                        I understand it.

                         

                        Best regards,

                        Kenji Takahashi