Uart Bit Sampling

[XiaoPing_Yang]

Hi Sir ,

    In the datasheet of CY95630H series , the sampling discribes as attched . I just want to konw ,when ' 1' or '0'comes ,

How many samples can be considered valid level ?

    Thanks .

[ShipingW_81]

The received data is sampled at a rising edge or a falling edge of CLK. Not sure the meaning of "How many samples"? 意思是同一个bit需要采样几次？

[XiaoPing_Yang]

Hi WangS_81,

     是的。规格书上，只是提了波形的最小宽度，没有提及在这个过程中采样多少次可以确认一个电平。

     Thanks。

[ShipingW_81]

看上去是否可以这样计算： 通过这个波形的最小宽度以及采样时钟频率确定在一个确认的电平期间内需要保持几次采样电平为高/低。