I believe that in all three examples there is some misconception regarding when "Set Data" takes place. On drawings provided it depicted somehow 90 deg to/from the rising edge of the Master Clock. But all CPU events "quantize" on the Master Clock, and "Set Data" is written with bus clock, taking place on the rising edge of the Master Clock as well.
I am less sure about "metastability" answer. My bet that in such case when "Set Data" and Clock_1 coincide at the same rising edge of the Master Clock (metastability event), the output of the Control Register should wait for the next tick of the Clock_1. According to the Datasheet it is "single-synched", which means one SC clock delay (single DFF register).
I updated my post above, I believe that red line is correct (one SC clock delay)
We would like to read the output of the control register in RTL(custom logic of UDB),
but the signal input to the clock of the control register is a signal synchronized to the master clock by RTL.
It is difficult that the timing of the details is not described in the data sheet.
Please find the control register working shown in below figures. (Architecture TRM '126.96.36.199 Control Register Operation') - https://www.cypress.com/file/123561/download
In original post the red line is correct for the third figure. As per above figure(21-33) if the Bus Write Clock(Master clock) and SC CLK(Clock) is at the same time. The Data bus change cannot come to 'To routing'(OutSync) in the same clock. The second flipflop in the above figure samples the old data on its first clock.
For response 4. The outsync will change on the first positive edge of 'clock'
Response 5 both the figures seems correct.
Conclusion: If Bus Write Clock and SC CLK positive edge comes at the same time, there is always 1 SC clock delay expected for the output.
If the SC clock positive edge is delayed by 'n' time from the Bus Write Clock. The output can change on first SC clock if the 'n' time is greater than the total propagation delay of first Flipflop. It will be safe to assume the propagation delay is less than the (1/HFCLK)maximum clock the chip supports.