2 Replies Latest reply on Jun 23, 2019 4:53 PM by RyYo_1406951

    PSoC4100SP:Slew Rate Chage

    RyYo_1406951

      Please answer below.
      The same question is written in English and Japanese.

       

      ・English
      https://community.cypress.com/thread/46805
      Continues the above thread.

       

      When changing slew rate, I change "PORT _ SLOW [25]" bit of "GPIO _ PRTx _ PC" register.
      Is there any other bit to change?

       

      If you look at the https://community.cypress.com/thread/46805 sample, you will notice that the value for "GPIO _ PRT1 _ PC" has been changed from "0x00000D8E" to "0x0200018E".
      I changed the value other than "PORT _ SLOW [25]" bit. Is there any reason?

       

      ・Japanese
      https://community.cypress.com/thread/46805
      上記スレッドの続きになります。

       

      スルーレート変更する際、
      "GPIO_PRTx_PC"レジスタの"PORT_SLOW[25]"bitを変更しますが、
      その他で変更するbit有りますでしょうか?

       

      https://community.cypress.com/thread/46805
      のサンプルを確認すると、"GPIO_PRT1_PC"の値を
      "0x00000D8E"から"0x0200018E"に変更しております。
      "PORT_SLOW[25]"bit以外の値を変更しておりますが、
      何か理由があるのでしょうか?

       

      Regards