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When calculating all of the timings in the MIPI receiver configurator, the CSI clock seems to be calculated as:
V-Total x H-Total x FPS x bitsperpixel
E.G. with 640 x 480 x 60fps x 8bits, with 1 lane, the CSI clock is calculated to be 73.73MHz exactly.
This seems surprising, as I would have thought there would be 8b/10b encoding, and perhaps some SoF / EoF / CRC bytes included too.
Why doesn't the CSI clock need to take these extra bytes into account?
Solved! Go to Solution.
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- cx3 mipi
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Edited:
As per Analysis of CX3 Video Timing Parameters – KBA226779
The minimum CSI clock required= (H-Active (in Pixels) × Pixel Depth) ÷ H-Total (in µs) ÷2 ÷ Data Lanes
i.e. = (640 X 😎 / 31.67 /2 /1 = 80.833 Mhz
Here 31.67 us is taken from Please help me understand timing of these MIPI waveforms .
In general, this value will be less than this number. Because 31.67 us includes the headers as well.
Encoding is optional in MIPI CSI-2. Error correction code (24-bit) will be part of data packetheader and 16 bit checksum in packetfooter.
You can see this in this figure.
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Edited:
As per Analysis of CX3 Video Timing Parameters – KBA226779
The minimum CSI clock required= (H-Active (in Pixels) × Pixel Depth) ÷ H-Total (in µs) ÷2 ÷ Data Lanes
i.e. = (640 X 😎 / 31.67 /2 /1 = 80.833 Mhz
Here 31.67 us is taken from Please help me understand timing of these MIPI waveforms .
In general, this value will be less than this number. Because 31.67 us includes the headers as well.
Encoding is optional in MIPI CSI-2. Error correction code (24-bit) will be part of data packetheader and 16 bit checksum in packetfooter.
You can see this in this figure.