The MIPI Multipacket example is shown below: (Source: http://caxapa.ru/thumbs/799244/MIPI_Alliance_Specification_for_Camera_S.pdf ). Here you can see that the VVALID is active from FS to FE. The timing of VVALID includes SoT, PH,FS,LS, PF,FE,LE,EoT. Similarly HVALID or DVALID.
Since you confirmed that the MIPI CSI is operating at 400 Mhz. Hactive time would be = 640*8 / clock / 2 (DDR clock) = 6.4 us.
By including the PH and PF, this time became 8.52 us in your case. You can consider the 23.15 us as Hblanking.
Answering your queries:
1. Does the H-Blanking period refer to the 23.15us "no data" period between the individual lines? In my example they are nearly three times longer than the active period!
2. Does the V-blanking period refer to the 1.32ms period between the 15.34ms active frame time?
3. Do I set the H-Blanking period to 23.15/8.52 * 640 ?
4. Do I set the V-Blanking period to 1.32/15.34 * 480 ?
5. Presumably I set the CSI clock to 400MHz?
6. Do I set the Pixel clock to more than (640+1740) x (480+42) x 60 ( = 74.54MHz)
Your calculations are correct for above 6 questions.
Can you please confirm whether you are able to see the video properly?
Also Probe HSync, VSync and PCLK_test signals of CX3 chip to findout the actual Hactive, Hblanking, Vactive and Vblanking.