3 Replies Latest reply on Jun 19, 2019 2:00 AM by YatheeshK_36

    IFCLK frequency in FIFO slave mode

    jega_3839511

      Hi all

       

      According to the EZ-USB Technical Reference Manual, the IFCLK pin can be driven at any frequency between 5MHz and 48MHz.

      In my application, the IFCLK is sourced from the external clock and it works well at 40MHz in slave FIFO mode. Now the problem is : when I set the external frequency to 30MHz or lower, the data read by the FPGA will be totally wrong.

      And I am sure that the external clock is present at the IFCLK pin before the IFCONFIG.7 is set.

      Is there any other details about the usage of the IFCLK ?

       

      Looking forward to your help soon!

      Thanks very much!

        • 1. Re: IFCLK frequency in FIFO slave mode
          YatheeshK_36

          Hello,

           

          Can you please send us the oscilloscope/analyzer traces for both 30MHz and 40MHz.

           

          Best Regards,

          Yatheesh

          • 2. Re: IFCLK frequency in FIFO slave mode
            jega_3839511

            Hello

                 The USB IFCLK is sourced from the inverted clock generated by FPGA which is woking synchronously at 30MHz. IFCONFIG = 0x03;

            The follwing  picture is  the oscill. waveform for 30 MHz. Yellow is the IFCLK and the blue is FD4.

             

                 But why the data lasts only half of a clock instead of a whole clock ?tek00016.png

            • 3. Re: IFCLK frequency in FIFO slave mode
              YatheeshK_36

              Hello,

               

              Please make sure that all the timing constraints are met. Refer to FX2LP data sheet "Slave FIFO Synchronous Write Timing Diagram" and Table 24 for the timing constraints.

              The FIFO data(FD) to clock(IFCLK) setup time should be minimum of 3.2ns and hold time should be minimum of 4.5ns which seems to be fine in the oscilloscope trace, please check if the SLWR to clock setup time has a minimum of 12.1ns and Clock to SLWR hold time has a minimum of 3.6ns.

              Make sure that the slave write signal (SLWR) is deasserted (made high) before the next positive edge of the IFCLK else the FIFO pointer will be incremented on each rising edge of IFCLK and unwanted data will be written to FIFO.

               

              Best Regards,

              Yatheesh